Hello All,

1) Place filtering on all inputs and outputs (series R and a cap to GND)
2) Avoid traces running over GND and power plane breaks.  You can play with
layer stackup to do this.
3) Place series R's and potentially capacitors (to gnd) on all clock
signals.

Paul


-----Original Message-----
From: Mamdouh Wahab [mailto:[EMAIL PROTECTED]]
Sent: Monday, April 09, 2001 5:56 PM
To: Protel EDA Forum
Subject: [PEDA] FCC and design for Manufacturability advice


Hello all,

    We are in the process of finalizing a design layout, however
we want to catch all unforseen surprises like meeting FCC
requirements and manufacturability issues.
Can anyone give us  recommendations where to go from here.

Thanks in advance

M. Wahab




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