Carl ,

What I have done in the past:   I have our engineer layout his design with a
TESTPOINT symbol on each net.  This can be done on each sheet or can be
attached as the last page(s) of the schematic. I create a surface mount pad
according to my  test requirements.  The pad will also include a keepout
circle drawn on one the mechanical layers so that I can observe the min
testpoint to testpoint spacing.
I design and route my board first without the TESTPOINTS. Then  I load the
netlist and now the testpoints points.     I move  one testpoint at time an
locate them on existing vias. and pads  only on  the side that will be
tested.  This method has proved flawless for me because I can inspect every
testpoint as I am placing them for clearances, and it insures that every
testpoint is accessible and can be identified.
When you are done generate a Pick and place  report , extract the TP data
and presto you have every location for testing.   And hopefully you meet
your test requirements.  Feel free to email if you have any questions

Mike Reagan
EDSI
Frederick MD
[EMAIL PROTECTED]


----- Original Message -----
From: Schattke, Carl <[EMAIL PROTECTED]>
To: Protel EDA Forum <[EMAIL PROTECTED]>
Sent: Friday, July 27, 2001 12:35 PM
Subject: [PEDA] Test point tenting on side opposite TP


> Hello,
>    Has anyone figured out a work around so test points will only be
exposed
> on
> the tested side and tented on the untested side (like under fine pitch SMT
> components)?
>    Editing the Gerber's is the only way I know to do this now.  :(
> I would prefer something that be reproducible after revisions are made.
>    Any news about a new version coming?
>
> Sincerely,
> Carl Schattke, C.I.D.
> Intel Corporation,  ACT
> Sr. Hardware Engineer ( PCB Design)
> 122 Saratoga Ave. Suite 100
> Santa Clara, CA 95052
> Office 408-556-3122
> Fax 408-261-5869
> 24 Hr. Ph. 888-204-3704
> Email:  [EMAIL PROTECTED]
>
>
>

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