On 08:08 PM 21/10/2001 -0400, [EMAIL PROTECTED] said:
>Hello,
>
>I've been tasked to implement to state machine using a PLD (written in CUPL
>language) that will replace a "Phase Comparator 2" PLL.
>
>I have the State equations (from a PLL data sheet) and I know how to use an
>analog integration scheme to mimic a tristate output of the PLL chip using
>two State machine outputs.
>
>I need to translation my state machine diagram into CUPL language. The protel
>help menus are not particularly helpful. Any guidance would be helpful.
>
>Thanks in advance
>
>Charlie Rich
>Lightwave Electronics

I found the documentation on state machine design in the on-line help 
useful.  It helps if you have designed state machines in other HDLs I guess 
but even so there was reasonable detail.

Have you looked at the SEQUENCE keyword in the help - I think that is 
it,  PLD is not installed on the computer at hand.  There are some examples 
as well from memory.

The basic structure is to define a state variable (bank of registers 
collected together to form a state variable with sufficient depth for the 
number of states) and then in the sequence you define the state transition 
conditions and the state machine output for each possible state.

Easiest method will be to find the examples and read the on-line help on 
programmable logic.

Ian Wilson

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