Comments in text below:

> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> Sent: Monday, 5 November 2001 12:07 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Net Transfer
> 
> 
> At 10:24 AM 11/5/01 +1300, Wayne Trow wrote:
> 
> >Ive got a design that was made a long time ago by someone 
> else and the pcb
> >has no net information associated with free primitives (traces).
> >
> >Updating from schematic doesn't seem to fix it. Thats with 
> "Assign net to
> >connected copper" checked.
> 
> This is a case where using Netlist load 
> (Design/NetlistManager/LoadNetlist 
> as I recall) instead of Update from Schematic may be easier to 
> troubleshoot. Create a netlist from the Schematic, then load 
> that into PCB.
> 
> A series of macros will be created. Right-click on the macro 
> display and 
> save it as a text file. Search the text file for Error messages.
> 
> One possibility is that components do not exist on the board, 
> instead there 
> are only free primitives. Yes, I've encountered designs like 
> that, done by 
> engineers who didn't want to take the time to create real 
> footprints, etc. 
> They checked the board by having two engineers work together 
> to mark it off 
> against the schematic. Of course, the whole thing would have 
> taken much 
> less time if they had done it right in the first place, but 
> reality does 
> not have to make sense....
> 

When I first started using Protel (Easytrax/Autotrax?) this was the way PCBs
were engineered at the company that employed me. The problem was that no-one
knew how to drive the software correctly. An update to V3 then 98 and a
training seminar sorted that out.

> By the way, in boards which have been checked in this way, I 
> have sometimes 
> found errors. Generally they were not errors that would cause 
> the assembled 
> PCB to fail, though they could drive a technician mad; gates might be 
> swapped or a series resistor-capacitor swapped, a bypass 
> capacitor might be 
> unconnected, etc.
> 

Oh yeah - we had plenty of those... and worse. I cringe when I look back at
some of my first designs.

> If the nets are not loading into the pads, obviously the process that 
> assigns nets from connected copper is not going to work. So 
> fix problems in 
> the netlist load first, then worry about connected copper. 
> One of the most 
> common problems is pad names not matching between the 
> schematic symbol and 
> the PCB footprint. Names must match *exactly*.
> 
> Once the pads are all correctly assigned nets -- you can 
> generate a netlist 
> from the board that can be compared with the original 
> netlist, if you want 
> to be sure -- you might then look for shorts. If two nets are shorted 
> together, some or all of the primitives in those nets may not receive 
> netlist assignments. You must eliminate those shorts.
> 
> (Netlist generation from PCB is of two kinds: one generates a 
> netlist which 
> reflects the actual connections on the board, i.e., what the copper 
> implements, the other simply dumps a netlist from what is 
> loaded into the 
> pads. I was talking, in the last paragraph, about the second 
> kind, from 
> which you could check pad net assignments independent of the tracks 
> connecting pads.)
> 
> Having primitives outside the workspace may also cause 
> troubles, but that 
> would be relatively rare.
> 
> [EMAIL PROTECTED]
> Abdulrahman Lomax
> Easthampton, Massachusetts USA
> 

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