Hi Wesley,

This is what I would do, if I understand what you described...

Make a physical clearance in the inner plane where you put the via so it
will not connect... 
If you are using power/gnd planes and not polygon fills then you need to
just put a fill or pad in the area on the negative layer where the via is,
and make it connected to no net... 
It will plot reversed as a hole in the plane... the via will not be close
enough to the internal copper to make the connection. If you are using
Polygon fills for planes, put a keepout area around the via and regenerate
the polygon fill. Hope that helps...


Bill Brooks 
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court 
Vista, CA 92083 
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 
mailto:[EMAIL PROTECTED] 
IPC Designers Council, San Diego Chapter 
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm


-----Original Message-----
From: Wesley Webb [mailto:[EMAIL PROTECTED]]
Sent: Thursday, November 29, 2001 7:56 AM
To: Protel EDA Forum
Subject: [PEDA] Padstack


Hi,

Can anyone tell me if it is possible make a via or pad that is connected to 
the Vcc net on the top and bottom layers only. TI do not want to connect it 
to the inner Vcc plane as the decoupling caps are on the secondary side of 
the pcb and I want the voltage to see them before the leg of the IC.

I tried making a pad and using the padstack to not connect to the middle 
layers but was not sucessful.

Any help would be welcome.
Thank You in advance.

Wesley Webb



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