That DOES work if its a Pad and not a Via...(only because you can't uniquely identify a single via other than by its size and hole if they were different than all the rest of the vias on the board. Place a free PAD out there and call it '1', connect the net to 'gnd'. Then you can define a rule for "plane connect" and set the "power plane connect style" filter kind to "PAD" and and look for "free pad 1" and set the Rule Attributes to "No Connect". This will make a clearance around the pad based on the clearance rules you have set up. Bill Brooks PCB Design Engineer , C.I.D. DATRON WORLD COMMUNICATIONS, INC 3030 Enterprise Court Vista, CA 92083 Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 mailto:[EMAIL PROTECTED] IPC Designers Council, San Diego Chapter http://www.ipc.org/SanDiego/ http://home.fda.net/bbrooks/pca/pca.htm
-----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 29, 2001 9:30 AM To: Protel EDA Forum Subject: Re: [PEDA] Padstack > Can anyone tell me if it is possible make a via or pad that is connected to > the Vcc net on the top and bottom layers only. TI do not want to connect it > to the inner Vcc plane as the decoupling caps are on the secondary side of > the pcb and I want the voltage to see them before the leg of the IC. Just make a design rule that says that pad is not connected to the plane. It works great. Vias are harder to make rules for so a free pad is probably better to use. Rob * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
