Hi, I have a problem with vias on a 6 layer board with a stack up like:
T --P-- 1 --C-- 2 --P-- 3 --C-- 4 --P-- B Among others a via type, from layer 1 to layer 4, witch is depending on the layer stack, were used. But some of the vias were only connected on layer 1 and layer 3. Our board manufacturer had problems with these ones, because these vias appeared without the pad on layer 4 in the Gerber files. In other words, there was just a metallized hole in the board. During the etching process these vias were destroyed. All vias and tracks were manually placed and routed. In DRC runs with Minimal Anular Ring Rule set >0 no violation were found. Does anyone out there know, how to fix this trouble or how to check the vias. Any help would be welcome. Thanks in advance. Regards, Matthias Trebeck Infineon Technologies AG Automotive Industrial AI MC AC EMC fon: +49 89 636 83244 fax: +49 89 234 723831 mailto:[EMAIL PROTECTED] **** VISIT US AT: http://www.infineon.com **** Mit freundlichen Gr��en Matthias Trebeck Infineon Technologies AG Automotive Industrial AI MC AC EMC fon: +49 89 636 83244 fax: +49 89 234 723831 mailto:[EMAIL PROTECTED] **** VISIT US AT: http://www.infineon.com **** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
