At 11:07 AM 11/30/01 -0800, Cliff Gerhard wrote:
>When I get a clean DRC, I can be confident that nothing was overlooked.  I
>have worked the other way, ending up with DRC errors and checking them off
>to make sure they are all were there for a reason.  Inevitably, one will
>slip thru and bite you (usually at the worse possible time).

This is why I highly recommend taking the trouble to track down and 
eliminate all DRC violations and all ERC errors and warnings. If you are 
going to take the time to verify that an error is spurious in some way, 
with very little more work you can eliminate the error, if you know how. It 
is worth doing.

At the schematic end, I always check for all unconnected pins and then pop 
a No-ERC directive on the ones that are truly intended to be unconnected. 
(The Error matrix default does not do this....)

The only exception where I leave a DRC warning is with primitives on inner 
layers; I place an outline track, say 50 mils wide, to back off inner 
planes from the board edge. Protel issues a warning, and the only way to 
suppress this would be to use a mechanical plane merge instead of putting 
the primitives directly on the inner plane (one mech layer could serve for 
all the inner planes; the planes would be plotted using different gerber 
setups, something that the CAM Manager now allows; essentially each plot 
can be customized if desired); that seems like a good idea to me, but I 
haven't done this....

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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