To add to Brad's note- I use keepouts to prevent polygon planes from pouring
in certain areas of my board.  I don't want poylgons under smt resistors,
etc. I want to be able to control where the polys go. the only way is with
keepouts on specific layers, and in certain areas. It's a nuisance to remove
the keepouts just to run a DRC. If you set a rule clearance to "0" for
keepouts, and then pour a poly, you get some very strange results. PCAD had
a nice way to create keepouts (that's not their exact name); the main fact
is that the keepouts didn't violate any DRC's! Does anybody remember the
exact name and use of keepouts in ACCEL/PCAD?
Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170

----- Original Message -----
From: "Brad Velander" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Wednesday, December 12, 2001 5:36 PM
Subject: Re: [PEDA] Keepouts & DRC


> Rene & others,
> it is timely that Sean raised this issue because I have been
> fighting with related issues. In my case I have a very complex board
outline
> where I have copied the board outline to the bottom layer and made it a
> keepout and control my polygon outlines with respect to the board edge.
> There are associated issues but I get lots of violations that I am trying
to
> eliminate with rules, seems to only work part of the time. I also believe
> that I have found a bug relating to polygons while trying to accomplish
> this, I will write about it in a day or two when the crunch is off.
> In my case I have a number of drill holes at points along the board
> outline. These drills are to relieve the board outline edge where the
> overlying matrix has sharp corners that a router cannot achieve. Thus each
> of these drill holes have no net, no plating, no pad (0mils). Each and
> everyone of them causes a violation with the keepout.
>
> The funniest thing is working over several variations of the PCB
> design, some rules work in one copy of the board and while making the
> variations to the next version the same existing rule will quit working
all
> of a sudden. I have also had the keepout lines showing violations along
the
> entire board outline because they are touching the keepout adjacent to
them.
> The listed violation lists the one keepout track segment and it's adjacent
> connected track as the other violator in the pair. Go figure.
>
> There are also other cases where a violation is not avoidable, so I
> am trying to devise rules which will eliminate those violations. Sometimes
> the rules work, sometimes they do not. At the moment I have databases
which
> have over 300 violations which seem to be indefinable in the DRC rules
> set-up, most all are related to the keepout. I have even tried a rule
which
> states the keepout spacing to anything else (Board) is 0mils, no luck.
>
> Sincerely,
> Brad Velander.
>
> Lead PCB Designer
> Norsat International Inc.
> #300 - 4401 Still Creek Drive,
> Burnaby, B.C., Canada, V5C 6G9.
> Tel   (604) 292-9089 (direct line)
> Fax  (604) 292-9010
> Website: www.norsat.com
>
>
> -----Original Message-----
> From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, December 12, 2001 8:06 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Keepouts & DRC
>
>
> You can draw a track manually over a keepout line.
> The DRC signals a violation and you ignore it.
> Is that what you want ?
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
>
> Sean James wrote:
> >
> > Is there any way to ignore or bypass keepouts during a DRC?
> >
>


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