I do high speed DSP designs and we have used 99SE recently for 5
different 12 layer dual TMS320C6711 designs with PC100 memory. I was forced
to use "POST MORTEM" analysis to see if the route could possibly work in the
first place. I wrote a "C" program that directly imported the Protel net
length/net list report and crunched the paths, calculating capacitance,
strip line inductance and trace resonance. I did not find out how to use any
real high speed design analysis tools that might be buried in 99SE
somewhere.(I gave up looking after finding out how poor the auto router
was!) The documentation is so poor that if there are any good design
analysis tools built in, they are buried from obvious usefulness.
        What we really need is "Hyper Lynx" or Cadence Allegro stuff which
costs a bundle. On the more positive side of things, I will tell you what
you can do with 99SE because we have done it by hook or crook! We have a
working 12 layer board that has twin TMS320C6711 DSP's and lots of PASIC's
and digitizers and fifos and 150mhz clock circuitry that digitizes and
compresses NTSC video and spits it across a PCI QUICK LOGIC PASIC in various
compressed formats. I used the auto router after re-designing every single
footprint so that there were adjacent fan out vias on every single pin. This
is the only way we could get the board to route 100%. I would then import
the net length report from 99SE into my "C" program and study the results. I
would then go move some parts around and re-route from scratch. Eventually
the numbers looked plausible to work. This was a poor man's way of getting
the job done. I did not like having to do it this way, but it is actually
amazing that it did work and took a WHOLE LOT LESS TIME THAN MANUAL
ROUTING!!! Basically, in one man-day, I was able to route and re-route the
board a bunch of times until the numbers fell in line.
        If anyone is interested in this little magic "C" program, let me
know and I will freely pass it around. There are no guarantees that it is
correct but it did make the elephants stay away!

R. Gordon Price
Director of Research Engineering
Loronix Information Systems, Inc.
Del Mar CA
(858) 523-9424

-----Original Message-----
From: Brooks,Bill [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, December 12, 2001 11:05 AM
To: 'Protel EDA Forum'
Subject: [PEDA] Signal Analysis ?

I received this question from an associate who is evaluating the Protel
Software and thought I should post it to the forum. Your thoughts? 
Do you use the signal analysis on Protel?  If so, how well does it work?
We're finally getting up high enough that we've started checking the
signals, so a couple of the engineering were wondering about that

Bill Brooks 
PCB Design Engineer , C.I.D.
3030 Enterprise Court 
Vista, CA 92083 
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 
IPC Designers Council, San Diego Chapter

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