But abd ul-Rahman,
        do you want to edit approx. 200+ lines and curves making up the
board outline to adjust them to some other offset for use as the keepout? I
didn't think so. I also have to do this for 4 variations in board outlines
where approx. 20 - 25% of the board outline is different.
        I would generate this in ACAD but then I have to get them imported
back to Protel correctly (that's a significant battle in itself), confirm it
is all there and correct. Then I have to individually change each element of
that outline to keepout because you can't globally change keepout status. So
no, I am not thinking inside the box!

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
#300 - 4401 Still Creek Drive,
Burnaby, B.C., Canada, V5C 6G9.
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Website: www.norsat.com


-----Original Message-----
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 13, 2001 1:02 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Keepouts & DRC


There you go again, Brad, thinking in the box.

Yes, the holes overlap the actual board outline. But there is no rule that 
says that the board outline is identical to any keepout track.

You want to keep track out of the holes, I'd think. In fact, you'd want a 
clearance between the holes and any track. So the keepout is somewhere in 
between the holes and the closest position for the track....


>As for Dennis' comment,
>         my comments were about the lack of DRC rule control, or even DRC
>rules working at all.

It has been suggested that an equivalent to No-ERC be created for PCB. This 
would be a device for suppressing one very specific error message. Move the 
primitives involved, the No-DRC suppression goes away. That's a rough idea, 
anyway.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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