I found similar types of problems as you when messing around with SI. A couple
of other
things I found useful is to just cut and paste a small section of the design you
want to simulate
rather than the complete board. It just takes too long ( but maybe my comp is
too slow as
well, dual P200, NT)

If the sim is done using only the first few periods of the waveform, it may lead
to false results
as the reflections and crap have not had time to bounce back and alter the
shape. Then
you have to mess around trying to zoom in to get a couple of periods on the
graph.

Only IC type components setup as in, out or IO and these appeared to work,
giving the sort
of waveform ringing you would expect from running  at high frequencies.
Specifiying a connector
type as connector  and the sim didnt work. Changing it to IC and changing the
IBIS models did
work. and the IBIS convertor also worked. When I tested it I pulled a model off
out companies
website and converted it. Actually the engineer who wrote the model also works
here and he
was interested in the results.

I suspect that the models for other components may not be correctly defined.
Maybe the next
version will have all the bugs fixed in it.




_______________________________________________________________

Clive Broome
IDT Sydney Design Centre        Ph:         +61 2 9763 3513
8 Bayswater Dr, Homebush        Fax:        +61 2 9763 3409
Sydney,  NSW, 2127              Email:[EMAIL PROTECTED]
Australia

_______________________________________________________________




That maybe is a clue, do connectors have IBIS models




"Fred A Rupinski" <[EMAIL PROTECTED]> on 12/15/2001 08:35:35 AM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:   "Protel EDA Forum" <[EMAIL PROTECTED]>
cc:    (bcc: Clive Broome/sdc)

Subject:  [PEDA] Integrity



Topic:  Signal Integrity Issues

I want to provide my clients the service of previewing and reporting the signal
integrity of prototype PCBs. In order to ascertain the veracity of the results,
I ran some simple trials (on 12" x 4" PCBs, using three separate folders):

1. A terminated differential pair between
two small connectors over a ground plane.

2. A simple passive backplane, top and bottom
signal tracks, ground plane, three power planes,
six 38-pin edge connectors.

3. A signal swapper with two DB9s and two hex
inverters, plus top and bottom signal tracks,
ground plane, one power plane.

My experiences and questions are as follow:

1. Terminated differential pair:

 A. Signal nets were always listed
 as 'supply'. I had to manually edit
 them to be 'data'. Is there a PCB
 or schematic setting which overcomes
 this?

 B. The connectors had to be changed
 to 'IC type' to get the waveforms and
 net screening to work. What's going on?

 C. The overshoot/undershoot DRs were
 set to 0.25 volts. The PCB was altered
 to yield a 0.50 overshoot/undershoot.
 The DRC lists this check, but does not
 report this error. Is there a reason
 and a fix?

 D. Is there a way to configure the test
 for differentially loaded operation? I
 had to use single ended loading.

 E. Is there a way to control the rise
 and fall times of the stimulus?

 F. After all of the integrity warnings
 were eliminated, a 'Confirm' window still
 advised that warnings existed. Why
 should this happen?

2. Simple passive backplane:

 A. Signal nets were always listed
 as 'supply'. I had to manually edit
 them to be 'data'. Have I missed a
 setting?

 B. The leftmost and rightmost connectors
 had to be changed to 'IC' to get the
 waveforms and net screening to work.

 C. Net Screening reported that the selected
 nets  could be not be analyze because
 connectors were attached to them, yet
 the waveforms were displayed. What does
 this mean?

 D. The overshoot/undershoot DRs were
 set to 0.10 volts. The backplane was not
 terminated resulting in a 0.25 volt
 overshoot/undershoot. Again, the DRC
 lists this check, but does NOT report
 this error. Is there a fix?

 E. Since a passive backplane has no ICs, is
 there a way to drive the connector directly?

 F. If so, is there a way to control the rise
 and fall times of the stimulus?

 G. Again, after all of the integrity
 warnings were eliminated, a 'Confirm' window
 still advised that warnings existed. Why
 does this happen?

3. Signal swapper:

 A. The integrity checks were successful
 at the tracks between the IC buffers.

 B. The overshoot/undershoot DRCs were also
 successful at the tracks between the IC
 buffers.

 C. I had to edit the DB9s to IC Types to
 get results (as in the cases above) at the
 input and output tracks.

 D. The 'Confirm' window advised that warnings
 existed. Continuing allowed the integrity
 check to proceed; otherwise a report was
 displayed, but NO warnings were listed.


At some point schematic layer routing directives ceased to work and PCBs would
no longer auto-route 100%. Running the database repair utility resulted in a
"Corrupted Beyond Repair" message:

 A. How does a database become corrupted,
 and how can this be prevented?

 B. What specifically is the definition of
 a corrupted database?

 C. How can a corrupted database be repaired
 manually?

Also:

 A. Is there a way to change waveform colors?

 B. Is there a way to print a single selected
 waveform?

 C. Is there a way to add a caption or text to
 a printed waveform?

Your experiences, answers and comments will be welcomed.

Regards,
Fred A Rupinski

PS Using 99SE SP6 (Windows files) Under NT4 WS (stand alone) SP6










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