Hello everyone
During my redesign of a quite compact Board, I changed the positions and
Footprints of some Components. After the most work was done I discovered there
where vias under some SMD-PADS. For these is a deadly thing during reflow
soldering, I should find out where these happened and change it.
I desided to run an DRC an the Board. Following Item-2118 in the Protel
knowledge-base I did the Edit | Design Rules setting design-rules for minimum
clearence to 5mil (and as a test 0mil)
A) OjectKind - Vias | B) OjectKind - SmdPads | Any Net
You can imagine my surprise when I found no vialations on these rule.
Also I
know there is at least one.
Protel-DRC returned:
| Processing Rule :
| Clearance Constraint (Gap=0mil) (Is a Via ),(Is a Smd Pad)
| Rule Violations :0
So I only set these rula aktiv, the others pasiv and there where al the
violations (,ore then I wanted to see...)
Now here is my question: had anybody else seen this behavior? For I can
not
believe it is the fault off Protel, can anybody help me to find out what I am
missing?
Thanks in advance,
Waldemar
Some more informations:
I am using Protel99SE on Win98, you can find my clearence rules below:
Polygon&PE Thru-HolePad Different Nets 4mil
Polygon&GND Board Different Nets 10mil
Polygon Thru-Hole Pad,Smd Pad, Fill Different Nets 15mil
Thru-Hole Pad,SmdPad Thru-Hole Pad,Smd Pad Different Nets 10mil
Thru-Hole Pad,SmdPad Track/Arc, Via Different Nets 8mil
Via SmdPad Any Net 5mil
Board Board Different Nets 5mil
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