Jeff Stout wrote: > Ok, I've finally got Protel's Altera PLD development system up and > running. Now I'm really looking forward to some solid development > with the Altera EPM7032 device. > > I configured the PLD compiler to produce PLA files, push the > "GO" button, and found another problem. Protel's output converter > for PLA files only outputs up to 254 characters; and wouldn't > you know it, all pin names are put on the same line. This device > has 32 inputs/outputs, so the last 12 outputs are left off the list with > the first of the those last 12 cut off in the middle. Like this: > > #$ PINS 24 Input_1:37 Input_2:38 Input_3:39 Input_4:40 Output_5:2 > Output_6:3 Output_7:5 Output_8:6 Output_9:8 Output_10:10 Output_11:11 > Output_12:12 Output_13:13 Output_14:14 Output_15:15 Output_16:18 > Output_17:19 Output_18:20 Output_19:21 Output_20:22 O > > There were suppose to be another 12 names at the end. > > AAAAAAAAGGGGGGGGGGGGGGGGGGGGGUUUUUUUUUUUUUU!!!!!! > > I've done several successful designs with Protel for the 22V10. Believe > me when I say that getting Protel PLD to work was never this hard before.
Yes, it is pretty clear from a number of aspects that when they called this PLD, they were thinking of devices like the 22V10 as the top of the line. I'm doing 10 - 30K gate FPGAs for a number of projects, and some of these devices have 100+ signal pins. I'm not even trying to use Protel for this. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
