On 11:50 AM 21/02/2002 +1000, Damon Kelly said:
>Yes, I would really like a "Tie Net" entity!
>
>Particularly (or most commonly) for the "analog ground" and "digital ground"
>situation. I set different nets in the schematic, but when it comes time to
>layout the PCB, the DRC spits the dummy when I tie the two grounds together
>at the star point.
>
>Does anyone have a work-around for this?
>i.e. keep the two grounds (AGND and DGND) separate, EXCEPT for the nominated
>tie point
>
>Damon Kelly
>Hardware Engineer


There are a few workarounds.  The one that I think is most documentable but 
sometimes subject to Gerbering issues is the Lomax Virtual Short.

Basic method: make a really small gap between two small pads (0.1 mil), 
give each pad a name and then create a special clearance design rule to 
allow such a small gap between these pads.  Issues to watch for are gerber 
rounding and aperture matching.  So set a tight apt matching tolerance and 
set gerber to include more than the standard 3 decimal figures.

Tell your board house that what the really small (0.1 mil) clearance is for 
and let them know that you do not want it resolved - you want them to 
manufacture this as a short.

I like this workaround, for now, mostly as it is possible to document the 
rule (with the rule comment) and the Gerbering requirements pretty easily.

There are other methods as well:
Use a mech layer to tie the nets and then include that mech layer on the 
particular layer plot.
Use the allow short circuits design rule (but this does not allow you to 
control where and in how many places the short should be).

There is a FAQ and this item is in there but the FAQ is not well known and 
there has been further discussion on the best way forward since the FAQ 
entry (I think).  Search the archive for previous discussions on this.

Ian Wilson

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