At 02:25 PM 2/21/2002 -0500, Robison Michael R CNIN wrote:
>i've got a negative (ECL) and a positive (TTL) power plane
>on a board i'm doing.  right now i'm figuring on a matching
>ground plane for each power supply, spaced close to the
>rail for switching capacitance.  here's the stack i'm
>thinking of:
>critical traces
>noncritical traces
>noncritical traces
>critical traces
>does this seem reasonable?  i have some semblance of controlled
>impedance with each trace layer referenced to a dc plane.
>other stacks suggestions are welcomed.

Since price is an object, you might be able to cut two layers by doing 
something like this:

split power

You'd have to be able to partition the circuits and you'd have to be very 
careful how you cross the plane split. You would want no critical traces to 
cross the split on layers 4 or 6, and layer 1 would be preferred to layer 
3. But this would normally be quite doable.

>but i need both the ground planes common to each other.
>can i EVEN have two planes called GND?

You can have two planes which have the GND net assigned to them. Normally 
you would do nothing else, all ground vias would connect to both planes. 
You might even add vias in some places to stitch them together more 
thoroughly. A summary of the principles involved is to watch where the 
return current will flow and keep the loop area to a minimum. Ideally the 
return current flows directly below the trace at a constant impedance, but 
when you switch layers with a via, the current will seek the nearest via or 
will use the interplane capacitance, and for this reason a better stackup 
might be

split power

The reason for this is that the interplane capacitance can be maximized.

In this case, traces on layers 1 and 2 can be controlled impedance, though 
the appropriate trace width will of course be larger on layer 1.

>   is having two ground
>planes a bad idea?  if two ground planes is not a bad idea,
>then how do i tie them together?  NOTE:  if i tie them together
>i would like to do it in a way that doesn't mess up my design
>rules check.  i've noticed that additional vias and traces
>added to a pcb outside the schematic can make the design rules
>check flag them.

Not if they are assigned the correct nets. To assign a net to a via, just 
place it touching copper with the appropriate net, and it will pick up that 
net. Then you can move it to final position. Of course, you can always edit 
a via to the net you want later, but this way avoids generating, even 
temporarily, any DRC markers.

As to two ground planes, you might have more than that in a complex 
stackup. Not a problem, except for cost, and sometimes the layers get too 
thin. It is easier to control impedance on wide traces (i.e., at a given 
impedance, the thicker the dielectric the wider the trace) because of fab 

>i have another question.  this is iffy, but i'm a heathen
>designer anyway.  this is just a proto board, and although i'd
>like controlled impedance, i don't want to pay for it.  SO,
>what i am thinking is that if i get an 8-layer board at the
>standard 62 mil thickness, that they are going to be just about
>forced to give me between 6 to 8 mils between layers, without
>me ever having to spec it.  does this sound right?

Better: you can specify the thickness of the material they use, if that 
does not add cost. Ask them what the dielectric constant of it will be. Or, 
if you are using a cheap fast proto service like Advanced Circuits where 
you can have any color as long as it is white, ask them what they will use, 
then control your trace widths accordingly. Sure, it won't be exact, but 
this is for folk music, isn't it?

(Actually, I know that Mr. Robison does electronics for a very serious 
employer, but I also understand that the applications are not mission 
critical, unless things have changed. If you need serious impedance 
control, you will have to pay for it, but many applications will not need 
that, even if they are high speed; and this is indeed an engineering 

Abdulrahman Lomax
Easthampton, Massachusetts USA

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