interesting infos and articles, are there these or similar articles into German 
somewhere in the web?

Harald



> -----Ursprüngliche Nachricht-----
> Von: DUTTON Phil [mailto:[EMAIL PROTECTED]]
> Gesendet: Dienstag, 5. März 2002 04:58
> An: 'Protel EDA Forum'
> Betreff: Re: [PEDA] controlled impedance traces ?
> 
> 
> Have a look at UltraCAD's website. Lots of useful info and a 
> calculator.
> 
> http://www.eskimo.com/~ultra/calc.htm
> 
> There is much to consider when designing high speed boards.
> Find from your fab shop the layer spacing of the build that 
> you are using.
> distance above reference plane and track thickness will produce your
> impedance.
> (only scraping the surface)
> hope this helps,
> 
> Phil.
> 
> 
> -----Original Message-----
> From: rimas [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, 5 March 2002 13:37
> To: Protel EDA Forum
> Subject: [PEDA] controlled impedance traces ?
> 
> 
> hi there,
> 
> i suppose this question doesn't have to do with protel 
> specifically, but i 
> was hoping someone could answer it for me or at least point 
> me in the right 
> direction.  (i'm not a full time PCB layout person by the way)  i'm 
> presently laying out a board with a big xilinx fpga and a 
> gigabit ethernet 
> phy chip on it.  the datasheet for the gigabit chip says that the 
> connections between chips need to be done with 50 ohm impedance 
> traces.  how do i calculate the impedance of a trace ?  it 
> seems like trace 
> width and stackup order are the only two variables i have to 
> play with.  i 
> am planning to have protos of this board made by advanced 
> circuits, in case 
> that makes any difference.
> 
> thanks for any help,
> 
> -rimas
> 

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