Hello Rene,

Indeed I agree with you. The behaviour was that a previously low distortion
(<-90dB THD and IMD) op-amp based circuit, when re-laid out on a new PCB was
displaying distortion at higher than -35dB. Removal of the power rail
decoupling caps fixed the THD, but is not a very ideal solution! The problem
was due to the ground returns for the caps being of too high an impedance,
and the current spikes were injecting garbage into the signal path. I tried
to simulate the behaviour but the macromodels don't show the distortion that
I was getting, so I wanted to see if a transistor level model would work
better for this. It was more of a question of interest than a need to solve
a problem. The problem solution is easy - one plane for cap returns, and one
plane for signal ground, joined at one place. That has fixed it.

As an aside, I have found the Protel simulator to be pretty accurate, with
the limited steps that I have put it through so far.

Steve.

> -----Original Message-----
> From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]]
> Sent: 28 March 2002 17:27
> To: Protel EDA Forum
> Subject: Re: [PEDA] Transistor level simulation models
>
>
> A simulation is only as good as the model. Depending on the
> experienced behaviour you might have to include this or that.
>
> What unusual behaviour did you experience ?
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com

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