Another solution, besides those already given, is to use, in the footprint, 
through pads the size of vias and with the same hole size, given the same 
net as the SM pad. You will have complete DRC protection....

Another solution which might be better in some ways is to add a test point 
(single hole) part, one on each unused pin. Once one knows how to copy and 
paste, it would be very quick to add these to the schematic, one click per 
pad or even several pads with a single click.

These will then be incorporated into the net list; an advantage is that 
they can each be given a number which can appear on the legend, making such 
changes easier to document and recognise.

There are also ways to speed up the PCB side of this, but I won't go into 
detail now.

Note that it is an advantage to be able to move the test or wiring points 
if routing requires it... You can move pads included inside a footprint by 
unlocking the footprint in the Edit dialog; but I'd prefer adding separate 
parts; the separate parts can be made into a Union with the flat pack to 
which they adhere, so they will move around together.

At 11:10 AM 5/23/2002 -0700, Embedded Matt wrote:
>I'm working on a layout with two quad flat packs.  A
>substantial number of pins on each chip have no
>connection.  Because of the difficulty of
>hand-soldering to fine pitch pins, I would like to add
>a track and a via to each unused pin for possible use
>I'm have two issues:
>1. DRC flags these extra tracks and vias as
>2. I get no protection from the design rules that
>specify minimum clearances and such.
>I think this must be a common problem.  Is there an
>easy way to fix this without changing the schematic?
>Protel 99 SE sp6.

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