To implement the equalize netlengths feature, you have to define a netclass with
the nets you want to equalize. Then go to Design Rules/High Speed/Matched Length
 and set the attributes. Depending on how much room on the board you have, set
the
amplitude and gap for the largest that can be fitted. Then run Tools/Equalize
Net Length
 a couple of times to progressivly add sections.

Usually a couple of runs are required as Protel only 'adds' 1 section at a time.
It works
out which net in the netclass is the longest and adds sections to the other nets
to bring
them up. The amplitude and gap can be reduced in later runs to have a finer
tolarence.
You can then do a DRC to check the lengths. It all works suprisingly well.



_______________________________________________________________

Clive Broome
IDT Sydney Design Centre        Ph:         +61 2 9763 3513
8 Bayswater Dr, Homebush        Fax:        +61 2 9763 3409
Sydney,  NSW, 2127              Email:[EMAIL PROTECTED]
Australia
_______________________________________________________________





"Joey Nelson" <[EMAIL PROTECTED]> on 06/11/2002 04:15:24 AM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:   "Protel EDA Forum" <[EMAIL PROTECTED]>
cc:    (bcc: Clive Broome/sdc)

Subject:  [PEDA] Equalize Net Lengths?



The online help for matched net length rules seems to imply that if I set a rule
for a set of nets and then run Tools->Equalize Net Lengths, that the shorter net
will be accordioned to make up the difference, space allowing.  But this does
not seem to be the case.  I've checked and the tracks are not locked, and there
does seem to be sufficient space, but whenever I run Equalize Net Lengths, I
simply get a design rule error.

Is there some trick to getting this to work?  It certainly seems like something
the router should do, and I should not have to do by hand.

Joey Nelson








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