I'd try splitting the pours: a large area pour with large track widths and
a large pour grid, plus small regional pours wherever the coarse-grained
nature of the large pour has clearances that are larger than you want.

John Haddy



-----Original Message-----
From: Michael Reagan (EDSI) [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 31 July 2002 9:33 AM
To: Protel EDA Forum
Subject: [PEDA] Copper pours on outer layers


Question to smartest of smartest designers out there:

Here is the delima,   we have a board appox 24 x 30  ( a very large
backplane) , many thousands of connections, every layer controlled
impedance.  The boards are used for high speed  tele comminications
switching and data monitoring.  ( No the the tele com industry is not dead).
The designs are as many as 28 layers, some approching .250 inch in
thickness,  a very expensive baord to design and manufacture.

On the outer layers we avoid placing traces, since we embed the entire
design,  The outer layer are  copper pours tied to gnd  to reduce EMI and to
maintain controlled Z on the next inner layer.  The copper is poured on both
the  top and bottom layers.

Copper pours of this size are poured last because they are time consuming.
The pours can take 4 hours, and even longer if they are not right the first
time.  Question to any of the best out there.....can we avoid a copper pour
and merge a gnd layer to the top?  Does anyone have a method or suggestion
to merge copper to flood the top layer.     Is there a quicker method?   We
are using 99SE on aa 1 gig cpu with 512 meg.

Mike Reagan
EDSI


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