Ok, time for a different tact . . .

Are you running any of your clock lines (etc.) over any "gaps" in the planes
directly underneath them? Such as in the case of a "split plane"?

If so, you are probably "infecting' the entire involved planes and
specifically the supplies on them, completely back to the point of
commonality.

Something such as that can and will produce a problem such as this.

Are you using "thermals" underneath the BGA?

If so, they can destroy what little there is of any "power" or "ground"
planes by turning them into "supper swissed swiss cheese", as opposeed to
the "standard swiss cheese" you normally have under the BGA. this can cause
the return path to have to deviate quite a bit as opposed to a trace closely
coupled to a plane it's entire length.

Do you have any, and I mean ANY, of the massive number of grounds going to
the wrong ground.

With systems that are using multiple supplies today, it is relatively easy
to mistakenly connect one "ANALOG" ground pin to a "DIGITAL" ground, and
thereby cause a short of the two grounds within the device itself.

A variation of this is where a device, such as an ADC for example, may
specify that it has seperate "ANALOG" and "DIGITAL" ground, so that you
design the board accordingly, only to find out that the device actually has
a direct internal short (less than 0.1 ohm), as opposed some real isolation
(say maybe 0.8 ohm or more). Here again you short the supplies right at the
place you really think you have isolation.

Anyway, there's a couple of  thoughts to chew on . . .

JaMi

----- Original Message -----
From: "Brian Guralnick" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, September 09, 2002 5:14 PM
Subject: Re: [PEDA] on topic supply SOS


> This is one of the decoupling caps between VCCINT 1.8v & GND.
>
> As you can see, the 1.8v dips down to 1.625.  This creates havoc with the
processing inside the Altera EP20K200E which has clocks
> running at 133MHz, 125MHz, 95MHz, & 24MHz.
>
> 16KB
> ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/NoiseVcc18-2ns.png
> 14KB
> ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/NoiseVcc18-4ns.png
>
> Here is my current decoupling caps for the 1.8v.
>
> 4 x 0.1uf smd 0805 ceramic.
> 3 x 470uf electrolytic.
>
> See the problem?
>
> I originally had 32 x 0.1uf, but some rush work with cut & paste at one
time about 2 month ago left me with this to work with.
>
> I need a temp fix where I only have 4 sets of access points around the
APEX part with nice Vias to 1.8v.
>
> I can't get my hand on the Wima caps, any other solutions, or,
recommendations?
>
> ____________
> Brian Guralnick
> [EMAIL PROTECTED]
> Voice (514) 624-4003
> Fax (514) 624-3631
>
>
>
>
>
> ************************************************************************
> * Tracking #: 669C079B7080074D869310AF5DDAB6BA8D1C81E2
> *
> ************************************************************************

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