Scott,
        this sounds like a basic problem. As Steve has asked, if you supply
some more details then we could suggest some more probable causes.
        First items to check, polygon net names (they must be different to
avoid each other), design rules (you must have a rule that the pours would
follow to avoid each other). On the design rule and netlist end, do you have
the generic board - board clearance rule, do you have net names assigned to
the polygon pours?

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification 



> -----Original Message-----
> From: Scott Ellis [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, September 11, 2002 4:28 AM
> To: Protel EDA Forum
> Subject: [PEDA] Overlapping Polygons in 99SE
> 
> 
> I have a number of polygons on a board. If they overlap the 
> second one poured ignores the fact that the first one is 
> there. Is this just a bug? If so is there a way to make 
> Protel do what is expected (i.e. not connect different 
> polygons together!)
> Or am I just doing something wrong?
> 
> Scott Ellis
> Manager
> Novatex Research - Excellence in Electronic Research & Development
> [EMAIL PROTECTED]
> 41 Yule Road, Merewether, Newcastle, NSW 2291, Australia
> Ph 0412 988408   Fax 02 49636058

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