Miker,

I belive if you were to _first_ place your via such that it only cuts
through the ground plane and not any other copper, then the via will
automatically picks up GND as its net assignment.   Now, if you start
placing your guard traces _starting from the via_ then those too would
automatically be assigned to the GND net.    If while doing all of this the
on-line DRC was enabled with "IGNORE OBSTICAL" then, there shouldn't be any
DRC violations when you are done.

I don't see any need to mess around in the schematic with special lib parts
and what-not.    I've just draw a dashed line (not wire) around the
circuitry that I wanted to show had a guard (very simple).

Hope that helped out
Dave Lewis







"Robison Michael R CNIN" <[EMAIL PROTECTED]> on 09/27/2002 07:01:24
AM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:    "'Protel EDA Forum'" <[EMAIL PROTECTED]>
cc:

Subject:  [PEDA] Guard Traces


Hello,

I've drawn a schematic and now I'm attempting to interactively
route the traces to match some old artwork, but I've run into
some guard traces that I haven't got in the schematic.  At
least I think they are guard traces.  They have a via to GND
at one end and follow beside another trace for a while, and
then simply stop close by the termination of the actual signal
trace.

To be honest, I don't really care about their electrical func-
tion.  However, we are attempting to as closely match the orig-
inal artwork as possible, so the are definitely going on the
board.

My question is how do I add these to the board without causing
a bunch of design rule errors in the end?  Right now I'm simply
laying the track and punching the via at the end and assigning
the via to GND.  I know the DRC is gonna hate this, and I depend
on the DRC to verify my design and I'd like to not have to sift
thru the DRC to decide what is a valid error and what isn't.  I
want a clean DRC at the end of my board design.

Thank you, Miker






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