Hello David,

The type of board you are designing is the type of board my company
specialises in.

Please have a look at my managers reply to your questions below!

I hope you understand the english and it helps :)

Paul Holland
PCB Designer
Synergy Board Systems UK Ltd.
ISO9001:2000 Cert. No. 3223/02
Tel: 0044 (0) 1522 520222
Fax: 0044 (0) 1522 531222
Mob: 0044 (0) 7799 048851
Web: www.synergyboardsystems.com

David Ponizil,

Let me introduce myself as a Designer of Semiconductor Test Interfaces for
the Semiconductor market, our company is Synergy Board Systems (UK) Ltd.
Here is how we try to answer your question:

Firstly the layers you have defined are OK:

                       Top layer   Signal
                       Mid1          GND
                       Mid2          Signal1
                       Mid3          GND
                       Mid4          Signal2
                       Mid5          VDD1
                       Mid6          VDD2
                       Mid7          Signal3
                       Mid8          GND
                       Mid9          Signal4
                       Bottom layer Pogo pins connection,decapling
capacitors trace.

This is a good stacking to create 50 ohms using stripline and with all our

The Basics:
If all signals remained on one PCB substrate layer and were routed adjacent
to a ground plane, there would be little need for an article on return path
control.  Power and ground planes form a tightly coupled return path for
electromagnetic waves propagating down a conductor.  Signal energy is
contained in the waveguide formed by the trace and the plane (or planes),
with minimal electric or magnetic field leakage to surrounding structures
and space.  This waveguide forms a differential circuit where return
currents in the planes mirror signal currents in the conductor.
In reality, a PCB rarely contains only one trace layer and one ground layer.
Real designs require many more layers for signal routing and power
distribution.  In designing state-of -the-art electronic systems that
operate at high clock frequency and edge rates, it is necessary to look at
all the places where the return path can be compromised, and determine valid
engineering and routing solutions for each.  These can be categorized into
the areas of trace stack-up, split plane, via transitions and connectors.

We do as many board shops do including ECT have our own processes for
creating 50ohms after etching, board press etc. giving a final 50 ohms
impedance measured as you say using POLAR instruments.
For example we use the following stacking for 1oz (35um) Copper thickness
which is best for performance boards because this reduces line resistances,
The stacking would vary if there was a need for 1/2 oz (17um) Copper which
is normally the case for tighter tolerances for 0.5mm pitch BGA's or less.

                       Top layer   Signal       This is a difficult layer to fully
control impedance however 12 Mils works
                       Mid1          GND
                Core 8 Mils
                       Mid2          Signal1    Trace width 6 Mils (In the
design 6.7Mils to allow for etch rates)
                Fill 8 Mils
                       Mid3          GND
                Core 8 Mils
                       Mid4          Signal2    Trace width 6 Mils (In the
design 6.7Mils to allow for etch rates)
                Fill 8 Mils
                       Mid5          VDD1
                       Mid6          VDD2
                Fill 8 Mils
                       Mid7          Signal3    Trace width 6 Mils (In the
design 6.7Mils to allow for etch rates)
                Core 8 Mils
                       Mid8          GND
                Fill 8 Mils
                       Mid9          Signal4    Trace width 6 Mils (In the
design 6.7Mils to allow for etch rates)
                Core 8 Mils
                       Bottom layer Pogo pins connection,decapling
capacitors trace 12Mils.

The above stacking will fit into a 0.125" thick board For Example Agilent
test head AG93000 and will if you calculate using a Polar calculator 45ohms
but after processes as said above we know through experience the final
measured value is 50-52 ohms.
I can not answer how ECT would handle this manufacture but the stacking you
sent looks familar to what would be requested by ECT, I once worked there
and they produce good boards as do we.  I was not aware they had a factory
in Belgium, their factory when I was there Arizona when I worked there.  The
only customer I remember of theirs was Alcatel Belgium, now AMI.
Hope this helps, we here at SBS will be happy to quote for the
manufacture/assembly or design of such a board including frame hardware for
the tester if you want to discuss it further.



-----Original Message-----
From: David Pon  il [mailto:[EMAIL PROTECTED]]
Sent: 01 October 2002 20:26
To: Protel EDA Forum
Subject: [PEDA] Board build-measurement impedance question.

I have question little of topic from Protel,but pleas anyway..... .
The Board build for the Loadbords(Dutboards)
are mostly 8-20layer(12-20 for Digitals).
Now I have the design with PBGA 1.27mm pitch 20*20matrix (4rows of pins,free
middle) ,the DUT(Device under test) is placed on middle of round loadboard.
Digital traces, GND,VDD1 and VDD2 are in middle layers
8mil width and 8mil minimum clearence on board 24mil between
digital channels traces and 12mil width on top layer(top is used only for
short trace aprox. 7-10mm)(201 separate traces/pins on DUT).The clearence is
increase for polygons on 30mils and lower in middle for DUT only on 8mil.
This is only little describing the loadboard.

My question is "If I will normaly request 50Ohms impedance +/-10%" ,and the
board build is set like:
                       Top layer   Signal- 12mil width
                       Mid1          GND-plane
                       Mid2          Signal1 -8mil width traces 50Ohms /8mil
                       Mid3          GND-plane
                       Mid4          Signal2 - 8mil width traces 50Ohms/8mil
                       Mid5          VDD1-plane
                       Mid6          VDD2-plane
                       Mid7          Signal3- 8mil width traces 50Ohms /8mil
                       Mid8          GND-plane
                       Mid9          Signal4- 8mil width traces 50Ohms /8mil
                       Bottom layer Pogo pins connection,decapling
capacitors trace.

How....How the manufacturing house will declare +/-10% impedance?!?
Becourse in reality the copper have some thickness and will be
to the FR4 material different, if all 4 signals layer will be used on same
place/point(mostly in middle-on DUT) and different if only 1signal trace
will be there(all this have influence for permitivity of fill...that mean in
end different impedance?!).
Pleas do samebody know how the manufacturing house make impedance
control/measurement?I saw same Pollar hardware equipment,but don't know how
they wanna measure 20cm trace lenght on board.... .:-).This board will put
to ECT
board house(Belgium)....but how works impedance control in reality....
that's is my question.
Maybee I like PCB designer have prevent 4 midlayer signals on the same
place,but then how right design  the BGA?Or I'm taking care for samethink
which is not relevant?
My point of wiev is PCB designer and Board house are together taking care
for impedance,but how it is in Board house side?(Of course most board houses
are saing: We do not measure impedance,this is samethink what PCB designer
should care.....).
Thanks for evry response.
Best regards,
               David Ponizil

PS:Pleas,excuse me from my poor English.

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