On 04:18 PM 4/10/2002 +1000, Ian Wilson said:
>   I would normally design my sch to have full net/port/sheet entry 
> connections with all the correct input/output types and top level 
> interconnections.  I would then do a full ERC with the most restricted 
> net scope and make sure all is OK. But when I go to the PCB I would drop 
> back to "nets and ports global".  I will also usually make sure that an 
> Update PCB produces only expected macros when I use *any* of the sensible 
> scopes.

I should just also mention that I have also done many projects without any 
wiring on the top level sheet, in which case I only use "nets and ports 
global" throughout the design process.  Some of these have had no ports 
within the project, just global netnames.

Brad, any chance of looking at the project?  (You could mask the IP by 
globally changing all Part Types to something silly and removing as much as 
possible such that the problem is still apparent.

I would like to look at the problem in detail if possible.

Ian

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to