could you please clarify:
when wishing to destroy the handles made by the synchronizer
do you save the PCB as ASCII or the SCH or both?

thanks

Dennis Saputelli


Ian Wilson wrote:
> 
> On 04:33 PM 4/10/2002 +1200, [EMAIL PROTECTED] said:
> 
> >Yeah, it seems to be pointing at a problem with the synchronizer when used
> >in "nets and ports global" mode.  I think Brad mentioned it worked ok if he
> >went via the netlist method (while using separate sheets).
> >
> >As I said in an earlier post using nets and ports global is the only time I
> >have experienced this.
> >
> >Regards,
> >Brendon.
> 
> I have been following this thread but have had no significant suggestions
> other than those already given.
> 
> My experience:
> 1) I have never seen this issue (duplicate nets in PCB)
> 2) I almost always use "nets and ports global" (see below)
> 3) I have been using the synchronizer since it first appeared, I do not
> think I have used Netlist Load since then except for some debugging of a
> synch problem for another user.
> (The solution in that case was to clear the hidden handles by Saving-As
> ASCII format.  The problem in that case was due to mixing the synch with
> net list loads - choose one and stick with it, or make sure you clear the
> hidden handles if changing about.)
> 
> I have yet to do a design where I have so many channels that I am tempted
> to use a full hierarchical sch structure (the P99SE system of flattening
> designs is not really maintainable).  I satisfy design re-use by copy and
> paste.  I would normally design my sch to have full net/port/sheet entry
> connections with all the correct input/output types and top level
> interconnections.  I would then do a full ERC with the most restricted net
> scope and make sure all is OK. But when I go to the PCB I would drop back
> to "nets and ports global".  I will also usually make sure that an Update
> PCB produces only expected macros when I use *any* of the sensible scopes.
> 
> I have seen a few cases of the synch failing - one was due to mixed use of
> Netlist load between synchs, the other was one component causing some odd
> macros.  Deleting and re-adding the component fixed the problem.  We could
> not easily go back to replicate the issue and the board could not be
> released for others to look at.
> 
> I certainly have never had to do anything like copy all the sections of a
> design to one sheet.
> 
> I wonder if there is a breakdown in the hierarchy of the system rather than
> the synch itself.
> 
> Brad, does/did the hierarchy look OK?
> You can get a report on the hierarchy.
> Does this produce the expected result?
> What about BOM reports from the SCH?
> Are they OK?
> 
> Does the problem persist after you save the Sch sheets as ASCII and then
> close and re-open?
> Does saving a particular sheet as ASCII and re-opening fix it (is the
> problem related to one sheet)?
> 
> I know you said the Netlist load seemed to work OK so some of these next
> ones may be pointless.
> Have you created a netlist and looked at it?
> When you create a netlist there is some options for tracing the netlister
> as it does its business.
> What do you see when you turn on tracing (and look at the reports)?
> 
> Ian
> 

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