Bryn,

The IPC has a calculator at http://landpatterns.ipc.org/default.asp

that can assist with the land pattern design.

But be warned: there's a fundamental flaw with IPC-SM-782 calculation
method that adds all tolerances together (thus assuming that every
parameter will be at worst-case condition at the same time) rather than
taking the root-mean-square of the tolerances (which is a more
statistically
appropriate calculation). The effect of this is that if you enter every
parameter at its full tolerance limits, you'll end up with a land
pattern
design that's far larger than it needs to be in reality.

I usually trim some values (e.g. side fillet=0) as a matter of course. I
also
do two designs with the calculator: one with all parameters at nominal
(no
min/max variation); and one with the full tolerances entered. I then
compare
the two and pick a middle ground based on experience and
manufacturability.

For example, the calculator will happily cough up lands that are so wide
that
manufacturing design-rule-violating solder mask slivers will result
between
adjacent lands.

For gull-wing type packages, I usually start with the assumption that
I'm happy
with 0 heel fillet when the IC pins are at minimum spacing, while I want
a toe
fillet of the same width as the thickness of the lead when the pins are
at their
maximum spacing.

There's also some fundamental differences between land patterns that are
intended
for wave soldering versus those designed for reflow (in general, reflow
patterns
can have smaller lands). This type of thing should be discussed with
your assembler
since they'll have lots of experience with what doesn't work.

Despite its flaws, IPC-SM-782 is still a useful document (the front
part, not the
cheat sheets in the back half) and I'd recommend that all designers at
least read
the text to understand the philosophyof land pattern design.

Hope this helps,

John Haddy

> -----Original Message-----
> From: Bryn Wolfe [mailto:[EMAIL PROTECTED] 
> Sent: Wednesday, 4 June 2003 1:09 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] metric footprint
> 
> 
> John,
> 
> Assume that you don't have any info from the mfg other than 
> the package 
> dimensions. How do you then come up with a footprint? Specifically, I 
> find that the dimensions requested by Protel are typically not the 
> dimensions provided by the mfg datasheet, so it can get confusing to 
> figure out where the pads need to be.
> 
> As an example, I've got a 8x8 QFP (specifically an FTDI FT232BM USB 
> chip) that apparently isn't a standard package. In going through the 
> Protel process of creating a custom footprint, the dimensions 
> given in 
> the datasheet tell the size of the plastic package and the 
> extent of the 
> pins, but Protel wants the distance between the center of the 
> pads from 
> one side to the other and the vertical distance between the the 
> centerline of the horizontal pins and the nearest vertical pin. These 
> calculations, at least for me, seem to take several tries 
> before I get 
> something that looks right.
> 
> Moreover, selecting a pad size seems arbitrary at first 
> glance, but I'm 
> sure there are good conventions for chosing the pad size. If 
> there are 
> rules of thumb for determining pad size, I'm interested in 
> knowing them, 
> so if you know of any, lead on.
> 
> Bryn Wolfe
> 
> John Haddy wrote:
> 
> >Try:
> >
> >http://tsc.jeita.or.jp/eds/DATA/PACKAGE/ED731120.PDF
> >
> >John Haddy
> >
> >
> >
> >-----Original Message-----
> >From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]
> >Sent: Tuesday, 3 June 2003 6:51 PM
> >To: Protel EDA Forum
> >Subject: Re: [PEDA] metric footprint
> >
> >
> >Is there no footprint given in a manufacturers datasheet ?
> >It just a minute or two to make this footprint, much faster than a 
> >websearch.
> >
> >Rene
> >
> >  
> >
> 
> 
> 



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