I'm not familiar with any current work reflecting this. (Doesn't mean
that I'm up to the minute with my reading though...)

IPC-SM-782a suggests (section 3.3.3.1) fillets in the range of:

Toe: 0.4mm - 0.6mm
Heel: 0.0mm - 0.2mm
Side: -0.02mm - 0.02mm

I've always been wary of excess heel fillet since, to my way of
thinking,
extra metal in this region must necessarily restrict the ability of a
lead to flex in accomodation of thermal stresses. Note that this is my
assumption rather than having a basis in any published work.

I note, though, that in the example land patterns in the back of
IPC-SM-782a
the QFP toe and heel fillets are generally about equal.

John Haddy

> -----Original Message-----
> From: Ian Wilson [mailto:[EMAIL PROTECTED] 
> Sent: Wednesday, 4 June 2003 10:00 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] metric footprint
> 
> 
> On 08:24 AM 4/06/2003, John Haddy said:
> ><..snip..>
> >For gull-wing type packages, I usually start with the 
> assumption that 
> >I'm happy with 0 heel fillet when the IC pins are at minimum 
> spacing, 
> >while I want a toe
> >fillet of the same width as the thickness of the lead when 
> the pins are
> >at their
> >maximum spacing.
> 
> 
> I thought I had read somewhere, or seen in a seminar or 
> something, that the 
> heel is the dominant fillet and the toe is less relevant.  If 
> this is the 
> case wouldn't you need to ensure a suitable minimum heel 
> fillet and let the 
> toe fillet reduce in length under worst case conditions?
> 
> Are there any current references on heel fillet v toe fillet?
> 
> Thanks,
> Ian Wilson
> 
> 
> 



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