My apologies, I jumped the gun earlier and sent in error.

I have carefully inspected the routes and no sign of loops anywhere. The
analyzer seems to have  particular problems with "T" networks. I have cured
one instance of this by removing the route, deleting the net, creating a
new net and rerouting it. Another net is failing and the screening utility
reports "cannot analyze Open Collector output". No mention of open
collector anywhere in the setup. I certainly haven't told it so. Another
computer, running Protel, was able to analyze this route after extracting
the appropriate IBIS buffers. It made no difference to the other failing
route that I mentioned!
Also, I see what you mean about veracity. The plot tools, screen utility
and DRC will produce wildly different results from each other. This is
partly explained by the note describing  worst case node analysis. There
again, I tried every node on some tracks and still got differing resullts.
I have been able to get some useful indicators but I am looking forward (
possible trepidation ) to starting up the PCB.


                      "Bevan Weiss"                                                    
                      <[EMAIL PROTECTED]        To:       "Protel EDA Forum" <[EMAIL 
                      .com>                    cc:                                     
                                               Subject:  Re: [PEDA] Protel Signal 
                      09-Jun-2003 11:12                                                
                      Please respond to                                                
                      "Protel EDA                                                      

This came up not so long ago.

Protel has problems with certain traces when they contain loops in the
Otherwise in the signal integrity module, you should be able to select the
nets and get a list of the components on the net.  From that you can change
the component model used.
It doesn't do too bad a job on particular nets.  however it's far from
faultless, and the results obtained should be taken with a grain of salt
(make sure you have a salt shaker on hand, you'll go through many grains).

----- Original Message -----
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, June 09, 2003 8:22 PM
Subject: [PEDA] Protel Signal Integrity

> I have been trying to get a report out using the SI tool to provide info
> for an SDRAM interface. I have IBIS models and some results look useful.
> All the same I am going nuts trying to sort out some less than well
> documented aspects of the process. An SI report (Menu >Reports>SI) tells
> that I don't have component models attached. I cannot find any reference
> attaching models. Some nets SI will analyze, some it will not. Again no
> useful documentation. After modifying the layout SI will not analyze nets
> that it was previously OK with. Any clues as to how to get this thing
> running properly.
> ( Incidentally 9000 or not, this is a case where some decent and honest
> documentation would help. If I can get the thing working I shall compose
> process document  on how to use it so as to stop colleagues from wasting
> time. If I can't then I shall be looking at Orcad 9 and SpecctraQuest for
> the next job. I agree Orcad is clunky but I know that it works from using
> it in a previous job. Also the Cadence Tech Support can't be faulted. It
> looks as though I was mistaken  to believe the Protel hype. For sure it
> doesn't tempt me to try DXP. )
> Robbie

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