You are quite right, it is possible to create tiny loops under pads
inadvertantly. This explains some of the problems. I carefully looked for
this yesterday and found two instances. This still leaves about 5 tracks
which SI was happy enough to analyze before modification but now will not,
including two which it reports as having open collector outputs.  Virtual
memory seems OK according to the W2K resource meter (ho hum). I shall
continue by looking for loops and renaming nets (as this does mostly work).

Thank you.
Robbie



                                                                                       
                                                    
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                      10-Jun-2003 08:06        Subject:  Re: [PEDA] Protel Signal 
Integrity - self help                                    
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> I have carefully inspected the routes and no sign of loops anywhere. The
> analyzer seems to have  particular problems with "T" networks. I have
cured
> one instance of this by removing the route, deleting the net, creating a

The loops could be under pads. I had this problem on a board and could not
find the loops at all. DXP pointed out the loop and where it was (x,y
coords). Sure enough hidden under a pad was a loop, which confuses the SI
algorithm.

Not sure on the rest unless the virtual memory is running out on that
machine.

Robert D. LaMoreaux
MTS Systems Corp.
Powertrain Technology Division
4622 Runway Blvd.
Ann Arbor, MI 48108
734-822-9696
Fax 734-973-1103
Main Desk 734-973-1111









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