Make sure that there are no pins on the net defined as open collector
outputs.  This would be the most obvious cause of the problem.  Other than
that, perhaps the model that you're using for a particular component (IBIS
or similar) has one of the pins on the net designated as an open collector
output.  Just another possibility.
For the other nets, I'm not sure what could be causing the problem.  Does it
give some kind of warning about them?


----- Original Message -----
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, June 11, 2003 7:52 PM
Subject: Re: [PEDA] Protel Signal Integrity - self help


>
> You are quite right, it is possible to create tiny loops under pads
> inadvertantly. This explains some of the problems. I carefully looked for
> this yesterday and found two instances. This still leaves about 5 tracks
> which SI was happy enough to analyze before modification but now will not,
> including two which it reports as having open collector outputs.  Virtual
> memory seems OK according to the W2K resource meter (ho hum). I shall
> continue by looking for loops and renaming nets (as this does mostly
work).
>
> Thank you.
> Robbie


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