The problems I am left with are just not consistent. The IBIS model
converter report does not give any instances of open collector and the
SDRAM docs don't indicate oc anywhere. Also I have got the same instances
on other pins and these screen OK. It would be nice to know what is really
going on in the SI tool. None of the calculation algorithms are documented.
I'm not sure that the screening tool actually looks at the buffer model
either. I notice that you get the same results before and after assigning
values to pins.
The only two screening error messages I have seen are "Can't analyze net"
and "Can't analyze net - open collector output". It doesn't identify a
node. Is there a menu where the type of pin can be specified? I have only
found a box in the pin properties dialogue which can be set to Source, Load
or Terminator. Default seems to be Load.
I think I may have a corrupted database or a damaged DLL somewhere.
Now here's another thing.  From "Utilities>Repair" has anyone seen a report
to say that the database HASN'T been repaired successfully?

                      Bevan Weiss                                                      
                      <[EMAIL PROTECTED]        To:       Protel EDA Forum <[EMAIL 
                      .com>                    cc:                                     
                                               Subject:  Re: [PEDA] Protel Signal 
Integrity - self help                                    
                      11-Jun-2003 12:01                                                
                      Please respond to                                                
                      Protel EDA Forum                                                 

Make sure that there are no pins on the net defined as open collector
outputs.  This would be the most obvious cause of the problem.  Other than
that, perhaps the model that you're using for a particular component (IBIS
or similar) has one of the pins on the net designated as an open collector
output.  Just another possibility.
For the other nets, I'm not sure what could be causing the problem.  Does
give some kind of warning about them?

----- Original Message -----
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, June 11, 2003 7:52 PM
Subject: Re: [PEDA] Protel Signal Integrity - self help

> You are quite right, it is possible to create tiny loops under pads
> inadvertantly. This explains some of the problems. I carefully looked for
> this yesterday and found two instances. This still leaves about 5 tracks
> which SI was happy enough to analyze before modification but now will
> including two which it reports as having open collector outputs.  Virtual
> memory seems OK according to the W2K resource meter (ho hum). I shall
> continue by looking for loops and renaming nets (as this does mostly
> Thank you.
> Robbie

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