At 09:59 PM 7/25/2003, Craig Scribner wrote:Here's our current documentation for this. Please let me know if it's unclear on any of the points that have been discussed.
<..snip..> Here are my comments, page references are to pages in the document.
p. 1. The term "net identifiers" to refer to the various relevant objects can be a little confusing. Some of these primitives do not establish a net name, rather they function like a wire. Ports and Sheet Entries do not assign any name to the net; what they do is to make a connection between primitives of the same name (in the case of Sheet Entry/Port combinations, the connection is restricted to connection between the Sheet Entry and the Port on the named sheet, not to other Ports of the same name that might be elsewhere in the project). They function just as if you ran a wire between the sheets; as you know, wires don't control the net name.
They (sheet entries and ports) can optionally name nets in DXP. In Abd ul-Rahman's very useful discussion that followed this text just remember that in DXP, Ports and Sheet Entries can, optionally, name nets.
Me, I am an untrusting soul - if I want to re-use a design I will rename nets wherever possible, and suffer the small delay it takes me to globally rename nets to conform to a new naming system, if required. More often the new project can inherit the old naming scheme and so there is little problem. It is rarer that I am merging multiple similar older designs where I have to resolve a naming conflict, so I don't worry about the effort spent doing so.
I *hate* reading schematics where D0 on one page may be something else on an another and worse, D0 on one page may *not* be D0 on another. So I will go a long way before accepting this.
Sch design re-use in my experience has been very much on the basis of cut and paste and re-work as required. Very much like re-use of software components. The cost in making a design (software component) sufficiently flexible that it can be re-used without change, is often, not always mind, more that the cost in simply cutting and pasting the concept, design basis, or even the bulk of the schematic - at least in my experience.
Now my way of working is no gospel, so each to their own. But for me, I label nets at every layer, on every page pretty much. Makes intent, design review, design validation and test easier in my opinion. It also provides more infomation to the ERC (in P99SE) and compiler (in DXP) so these are better able to warn of unintended problems. Since changing the naming scheme of a re-used section of a design is a once-off operation, but production test is a per item operation you can probably guess what I like to optimise.
Thanks Abd ul-Rahman for a very comprehensive summary, Ian
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *