Hello fellow designers,

I just ran (again) into asomething weird concerning the online DRC of P98SE/SP6.
It may
I have a general rule stating that the minimum distance between a hole (via or pad) and an SMD-pad must be 8 mils, regardless of net. Handy rule, prevents solder loss during reflow. It even works.....:)
Now I have a few (SMD) programming pads on the board, to be used with a special connector. No SMD component will ever be fitted onto those pads, so solder loss is no problem. I want to be able to put vias in those pads, so I made a special pad class "non-SMD" and made all the programming pads a member of that class. Next I made a rule stating that members of pad class "non-SMD" do not need any clearance to holes (min clearance = 0).


Alas, the via and program pad both get a clearance violation ON THE RULE THAT STATES ZERO CLEARANCE ! I know it is that rule, because all other rules (including the solder loss prevention rule) are switched off. Even negative clearances (great or small) produce a violation....
When I ask what rules apply to these primitives I find that the "non-SMD" rule DOES apply....


Clearly there must be something wrong with the understanding or interpretation odf rules, be it mine, Protels' or both. Is there anyone among the expert users who can explain this?

As always, any help or insight is greatly appreceated.


Leo Potjewijd hardware designer IE Keyprocessor bv.

[EMAIL PROTECTED]
+31 20 4620700



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