> -----Original Message-----
> From: Laurie Biddulph [mailto:[EMAIL PROTECTED] 
> Sent: Monday, October 27, 2003 6:20 AM
> Subject: [PEDA] Joining nets
> We have a pcb that has both analog and digital circuits and 
> consequently we have assigned a ground to each type (AGND and 
> DGND). I need to join both of these to a common point on the 
> pcb which is the power supply circuit common (GND). How do I 
> join these three nets without using a wire link or other 
> connecting component - ie I would like to tie all three nets 
> together on the schematic and pcb.

I have attached some messages from the archives below including some
links to yahoo groups that have some files there which will help you.

As a point of interest, DXP supports this as a standard feature called
'net ties' If it is a feature high on your wish list then DXP may
benefit you and it would be worth downloading the DXP user manual have a
read at your leisure.

Best Regards

John A. Ross

RSD Communications ltd
WWW    http://www.rsd.tv
> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] 
> Sent: Monday, July 16, 2001 1:38 AM
> To: Protel EDA Forum
> Subject: [PEDA] Connecting grounds / virtual short
> Because the question frequently arises of how to connect two or more 
> grounds while maintain DRC and the separation of the grounds 
> except at a 
> single point, and because the instructions as to how to do 
> this can be 
> misinterpreted, I have uploaded to the protel-user filespace 
> a PCB file 
> with two virtual short footprints in it, two grounds which 
> are shorted by 
> the footprints, and a Design Rule which allows the close 
> proximity which is 
> the key to this method. The gap is 2 microinches and the 
> design rule allows 
> 1 microinch for that footprint.
> The file is in the filespace at

and the direct URL for file download is

Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433

> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]
> Sent: Friday, 22 February 2002 5:08 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Tie compoents(Ex: RF footprints)
> At 01:10 PM 2/21/2002 +1100, Ian Wilson wrote:
> >There are a few workarounds.  The one that I think is most 
> >documentable but sometimes subject to Gerbering issues is the Lomax 
> >Virtual Short.
> Note that Lomax himself now considers as at least equally satisfactory

> the use of mech layer shorts merged in the gerbers through CAM Manager
> definitions (which can be named, helping with documentation for future
> generations), the shorts being part of a special jumper
> component, just as
> with the virtual short.
> Note that Schematic control of the short is a very important part of 
> any solution. Schemes which do not automatically create and separate 
> nets except at one point, the visible and controllable short between 
> nets, do not satisfy this criterion; specifically this would be an 
> argument against the modification of split planes as some have used.
> >Basic method: make a really small gap between two small pads (0.1 
> >mil), give each pad a name and then create a special clearance design

> >rule to allow such a small gap between these pads.  Issues to watch 
> >for
> are gerber
> >rounding and aperture matching.  So set a tight apt matching
> tolerance and
> >set gerber to include more than the standard 3 decimal figures.
> It is best if the pads in question are part of a jumper which appears 
> on the schematic; the whole process becomes automatic at that point. 
> Want a single-point ground? Put a single-point ground jumper on the 
> schematic. With the virtual short you will need to set a design rule 
> allowing the pads of that component to be so close to each other; with

> the mech layer solution, you still need to set up a special gerber 
> definition and, preferably, to name the mech layer or layers used 
> appropriately.
> The gap should be smaller than 0.1 mil in my opinion. I've used 0.002 
> or 0.004 mil. Protel can get a little flaky in the sub-mil region, so 
> one may need to experiment (examples have been given in the past of 
> sizes and definitions known to work).
> PCAD has tienet polygons. I consider that solution, as far as I 
> understand it, as inferior to either of the workarounds we have at 
> present.
> I've described in the past various alternatives, I think, as to how 
> Protel could make this a directly accessible feature, instead of 
> merely a workaround. Instead of going down that road again, I'll just 
> state what I consider desireable.
> I want to place a symbol on a schematic; it may have any number of 
> pins, and these pins will be kept separate for netlist generation. 
> However, the footprint which is associated with this symbol may have 
> pads which are shorted together without creating any DRC error.
> This, I think, would actually be quite simple to implement, it is 
> really only a little jiggering with the DRC routines. Perhaps the 
> routines would recognize something about the name of the symbol, in 
> the type field perhaps, since that is fixed to be generated from the 
> symbol name, which allows shorts between the nets of the pads to take 
> place within the pad areas, whether by the pads themselves shorting or

> by track connected to the pads (provided that they only short within 
> the pad area, not anywhere else). No special rule should be needed, 
> because it is extra work to create
> such a rule and errors may take place during that. More than one name
> should be possible for this symbol, so perhaps the name would have a
> controlled prefix, such as PCBSHORT.
> Protel support is distinct from Protel engineering. While we would 
> wish that support personnel would read and be familiar with this list,

> I don't think that they are at this time. I might be wrong about that,

> at least with regard to some. I've many times said that it is 
> completely natural and to be expected that this list can provide 
> better support than Protel; I would suggest, in fact, that Protel 
> abandon much of its direct support and
> direct the funds freed up by this to software maintenance and
> development.
> Basically, issues that were not resolved quickly on this list
> would then be
> referred to support personnel, who would be very closely connected to
> engineering.
> This list generally answers questions more quickly than Protel support

> could possibly manage unless they were to throw a *lot* of money into 
> the effort. And that would be silly.
> Abdulrahman Lomax
> Easthampton, Massachusetts USA

> -----Original Message-----
> From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] 
> Sent: Monday, December 16, 2002 7:03 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Virtual Short
> Mr. Wilson has ably answered the questions, I have a little to add.
> At 08:26 PM 12/15/2002, you wrote:
> >On 08:44 PM 15/12/2002 -0400, Tim Fifield said:
> >>Can anyone explain the Lomax virtual short used for a GND 
> neck and how 
> >>it would be used on an internal layer with 2 polygon 
> planes? Can this 
> >>be used to result in no DRC violations? Also how do I keep 
> the planes 
> >>say 10 or 20 mil apart if allow for them to be much closer in the 
> >>design rules for the virtual short?
> >
> >Consider making the shorting neck a component.  Then you can 
> apply the
> >tiny clearance rule to just this component.
> I *highly* recommmend making the short a component, because 
> then short 
> becomes schematic-controlled and self-documenting. You or a 
> future designer 
> can't forget about it without deleting the component from the 
> schematic. 
> (There is a device for keeping the component from appearing 
> on the BOM, as 
> I recall one simply leaves the TYPE field empty. The same 
> device is used 
> for grounded mounting holes, for example.)
> >Or you could position two rectangular pads close together, 
> giving them
> >suitable names.  Then you can restrict the micro-clearance 
> to just these 
> >named pads.  Then track your neck in and out of these pads 
> as you wish.
> This would work, but I see no good reason to avoid using a netlisted 
> component. It is "set and forget."
> >The general poly clearance is then preserved.
> Either way. It is simplest, however, to set up a component 
> scope clearance 
> rule. Note that pad sizes and shapes should be such that the 
> connecting 
> tracks do not create a clearance violation in themselves.
> >>Should the board house be made aware of the virtual short 
> so they do 
> >>not remove the neck?
> >
> >Yes.
> The one known problem with the so-called Lomax virtual short 
> is that gerber 
> generation under some conditions can break through the 
> multiple defenses 
> against open copper, which, when combined with an eager 
> fabricator's desire 
> to "fix" problems without consulting, can cause an open. So, 
> yes, if you 
> are going to use this technique, telling the fabricator can't 
> hurt. "the 
> two pads of JP27 are to be shorted together, not isolated."
> Or one can use a different technique which I have myself come 
> to favor:
> Create an n-pin shorting component and place it on the 
> schematic. (n is the 
> number of nets to be shorted together at a single location, 
> as with a star 
> ground). The footprint for this component has n pads with 
> normal clearance. 
> On a dedicated mechanical layer, add track to the footprint 
> which shorts 
> the pads. Name this layer "shorting_jumpers". So when the 
> footprint is 
> called up it will automatically carry with it the shorts; but 
> the shorts 
> will not be seen by DRC as being copper.
> Then remove one of the copper layers from the regular gerber plot 
> definitions and create a special plot definition for that 
> layer; merge plot 
> the shorting_jumpers layer with that copper layer. I 
> recommend using an 
> outer layer (Top or Bottom) because it becomes possible to 
> cut the short 
> for test purposes. The pads for the same reason should be 
> through-hole pads 
> if possible; I'd use Berg pins/shorts for the flexibility of 
> being able to 
> add a regular shorting jumper during development.
> One of the beauties of Protel 99SE was the provision of 
> multiple gerber 
> set-ups, all of which can be generated simultaneously with a single 
> command. This is also useful, for example, with making 
> assembly drawings or 
> other drawings with format, where different mechanical layers 
> are merged 
> than one might use for, say, the fabrication films, where 
> full drawing 
> format is an expensive and useless addition.
> The "virtual short" was invented before we were given the special 
> plot-setup facilities....
> PCAD has a device called a tie polygon, which is a polygon 
> with multiple 
> net assignments. However, this is an inferior solution, in my 
> view, to 
> either of the above, unless perhaps the tie polygon can be 
> made part of a 
> footprint and thus provides the same kind of automatic 
> schematic-driven 
> control as these two techniques.

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