Bagotronix Tech Support wrote:

Has anyone ever successfully used Protel's PLD/FPGA features with a vendor's
(Xilinx, Altera, Lattice, etc.) toolsuite and gotten usable results? Was it
worth the hassle? I ask because it is usually better to use the vendor's
fitting, place, and route software than some 3rd party thing. I wonder if
Nexar will be another Altium product that is announced to much hype, driving
upgrade purchases, and then quietly dropped (remember PeakVHDL?).


I'm still on P99SE/SP6, I can't imagine moving once again to a new (major) version.
After three major tries, consuming several weeks each, I have actually done it!
There's no reason to do HDL work in Protel at all. But, for schematic FPGA work,
the Protel schematic entry is pretty good. I have to admit that the Xilinx schematic
editor is better integrated with the schematic/FPGA libraries, however. But, the
actual symbol and wire management of the Xilinx schematic package is so bad as
to be laughable! When you get over 10 simple gates on a C size page, it starts
doing wierd stuff of the "you can't put a wire there, it is too close to something else"
sort. I like to put a lot of stuff on a few pages, rather than having 3 gates on each of
300 pages. Protel allows making some VERY dense pages.


I tried making Xilinx XNF files years ago, and found that Xilinxc would not accept
the XNF files, giving a fairly specific message with line numbers for the syntax
error. I sent this to Protel (this predates Altium) with no response whatsoever.


I tried exporting EDIF files from Protel, and this came close to working, but the
EDIFs it output needed a LOT of hand editing to make them work. Way too much
to make this practical, without a program to do the editing, and that program would
not be real simple.


Then, I discovered thet Protel99 would output a VHDL file! Is this in the manual
or anywhere else? I discovered it totally by accident when scrolling through the list
of supported schematic export formats. This almost works without any changes in
the files at all. The only discrepancies are :


1. You need to manually add a definition and call-in the schematic symbol library,
that takes 2 "boiler-plate" lines in every VHDL file.


2. If you have user-defined symbols that reference schematic pages, the VHDL file
will have a port definition for each instance where the symbol is instantiated on your
schematic page. It should only have the port definition once, just like is does correctly
for symbols that come from a library.


These are pretty easy to edit by hand in a few seconds. Xilinx likes the VHDL format,
and generates good code from it. Errors in the schematic that produce illegal syntax
or errors on translation are pretty easy to follow back to the offending schematic,
although this is not seamless or automatic. The way Xilinx wants top-level pins to
be defined is different from what Protel wants, so the Protel ERC is not very useful.


This is a bit of extra work to go through, but the Xilinx schematic tool is **SO BAD**
that it is worth it.


With some fooling around, the PLD simulator is also usable, especially for checking
small sections of a design. In some ways it is a lot easier to set up a very quick check
graphically than Xilinx's MultiSim graft, which is a pretty ugly external grafting-on,
something like the way Protel did the CCT Specctra auto-router.


If anyone wants more details on this, I can provide a bit more detail.
It is only about 2 months ago I got this to work at all.

Jon



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