Graham Brown wrote:
Hi all, merry Christmas,
I have a board with an internal plane split between +5v and +30v. I inadvertently placed a via, belonging to the 30v net, right on the separating line, thereby bridging the two power nets. P99SE/SP6 did not find this during drc. Is this a limitation of Protel or of my menu-digging skills?
It appears to be a bug. I've just been lucky and not had a board go out for fab
with one of these, yet. If the via is totally in the wrong split plane region, it
will usually cause a reliable DRC error. Sometimes, I think, it will still
cause an error, depending on the exact placement of the via. Note that many
board manufacturers add additional "blowout" around the plane regions and
non-connecting through holes toimprove their yield. This is more likely to
cause thin areas in planes to become isolated, or cause a single split plane to
end up as two regions. But, in any case, Protel is not aware of that modification,
and can't predict the results when the fabricator does that expansion.
It is a pretty good idea to import the Gerbers and view them one at a time
(you can gang import them and then use shift-S to see the layers individually).
If you scan along the split plane boundaries, any thermal connection will be pretty
obvious. Any via (or pad) that doesn't connect to either plane should have a
blowout pad that just makes the gap between the plane regions bigger at that
spot, so those shouldn't be a problem even if right on the boundary.
But, you say your problem was a via. That normally would not have a thermal
connection, just a hole drilled into the plane. If you make the border line of the
planes larger than the hole diameter, then you should not get a short between
planes. (You'd get a no-connect for a via centered in the gap between planes.
That would at least be easier to fix.) But, this is also not easy to spot in the
Gerbers, as the direct plane connects do not show at all in single layer view.
I suppose you could select the power layer as the current layer, and enable only
the power layer and the multilayer, display vias only, and check the borders
But, I think making the split plane boundary track width wider than any reasonable
through hole is the best policy, and how I always do things. If both boundary
tracks are .020" wide, and you don't overlap them much, you should be pretty safe.
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