I agree, but when it comes to "Planes" you do not have a choice on "Copper
Coverage" and it's the Plane Layers that will cause the most damage if they
have unbalanced copper thickness coupled with unbalanced construction. 

I agree with your point on "Minimal Copper Traces". That's why I do not use
the Specctra "Batch" Autorouter anymore. It seems as though it dumps twice
as much copper on the trace layers (and twice the number of vias). I would
rather use an "Interactive Manual" router (and Specctra has one) to reduce
trace length and via count.


Tom Hausherr
PCB Libraries
CEO, Director of Technology
858.592.4826 Phone
847.745.0450 Fax
Website: http://www.PCBLibraries.com & http://www.PCBYellowPages.com

-----Original Message-----
From: Igor Gmitrovic [mailto:[EMAIL PROTECTED] 
Sent: Wednesday, July 21, 2004 10:54 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Board warpage?

Maybe it could be called 'Balanced Copper Coverage' rather then 'Thickness'?
Or 'Track Density'? 'Thickness' is rather ambiguous in this case. My goal is
always to take off as little Copper as possible. It prevents warping and
improves EMC performance. It is good for the environment as well, especially
in places where they pour the chemicals directly into the drain.


-----Original Message-----
From: Brian Guralnick [mailto:[EMAIL PROTECTED]
Sent: Thursday, 22 July 2004 10:54 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Board warpage?

>The solution is "Balanced Copper Thickness" throughout your design.
>Tom H 

Using a dummy polygon plane on each layer usually does a fine job, but,
don't expect repair de-soldering to be easy with so much copper sinking the
heat away from your application point.

Brian Guralnick

  ----- Original Message ----- 
  From: Tom Hausherr 
  To: 'Protel EDA Forum' 
  Sent: Wednesday, July 21, 2004 1:53 PM
  Subject: Re: [PEDA] Board warpage?


  I've seen every kind of layer stack-up imaginable.

  Board warpage is mainly caused by the uneven distribution of Copper

  If you have one plane that is out of order and call out 70um Copper
  Thickness (2OZ) your board will warp when the heat is applied either
  fabrication lamination our plugging your assembled board into a voltage

  The solution is "Balanced Copper Thickness" throughout your design.

  Tom H 

  -----Original Message-----
  From: Harry Selfridge [mailto:[EMAIL PROTECTED]
  Sent: Wednesday, July 21, 2004 10:28 AM
  To: Protel EDA Forum
  Subject: Re: [PEDA] Board warpage?

  It isn't an odd number of PAIRS that causes problems - it is an odd number

  of LAYERS.  There are some advanced fab techniques that can reliably 
  produce boards with odd number of planes or odd number of signal layers; 
  however, there are very few fabs I would trust to do it.  You can
  get away with odd number stackups, but it will eventually bite you in the

  Six layers is a common balanced stackup - provided there are an even
  of planes, and even number of signal layers with reasonably distributed

  At 01:56 AM 7/21/04, you wrote:
  >Some say that an odd number of layer pairs can cause problems, indeed we 
  >had problems with 6 layers at first, though we now use 6 layers to great 
  >success.  Problems with that were caused by bad process control, not the 
  >design (though the manufacturer tried to blame design at the time!!)

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