It looks pretty darn good. I mostly have nitpicky details that I think
you should not change until the next board rev. There are a few details
I think you do need to change, they're marked with **WARNING**.

# In General

1. You put all your components on one side. This is usually a very good
thing. However, in this case, I think I would have put some components
on the back. For example, bypass caps and other passives. Not a big
deal, and it prevents you from "skilleting" - but since we use a toaster
overn, that's ok with us. In the worse case, soldering on a few 0402
components to the underside of the board isn't the worst thing, although
it is a pain.

2. It's often useful to have a outline layer all by itself - so I might
move the outline to a separate "outline" layer. That said, I always
forget what AC wants, so probably ignore this.

3. I don't see many test points, but you have enough vias to keep you
out of trouble. That said, I'd want to do a careful search to make sure
that there's a decent test point access, especially off of U9, since you
don't have access to any of those pins. That all said, I don't see any
truly buried traces.

4. Usually people use "top" and "bottom", not "front" and "back", but
that's just me and my OCD.

# Silkscreen

1. The lettering on the silkscreen needs to have thicker line widths (AC
has a design rule of 0.006", and it usually applies to everything,
including silkscreen). Currently you're at 0.005".

2. After making the lines thicker, I'd try and make the letter shorter,
so they can be better placed.

3. Many of your silkscreen labels will be clipped by the process
(especially by vias), or covered by their components. Not a big deal,
but a pain sometimes when debugging.

4. You don't have outlines around your passive components, which means
that it might be possible to make the classic "90 degree off" error when
placing them. I strongly recommend in the next design you add those in.

5. The silkscreen outlines for your ICs should be the actual size of the
IC package, including their pads, and indicate which is pin 1. You have
some of them outlines, some of them have pin 1 markers, but it isn't
consistent. This gives a visual read as to how big the components are,
how they're placed, and how closely they're placed. **WARNING** For
example, I'm not positive that U5 doesn't actually touch U6. If you read
the microchip data sheet, I calculate a maximum of 1.71 mm from the
center of the edge pins to the outside of the package. If U6's outline
is correct, then they may actually touch. That's bad, since they may not
actually fit, or they may push each other around when reflowing. U3 to
U4 is another example. This is almost not worth a warning since you've
probably done your homework here, but I think it's a very important
sanity check. Again, silkscreen on top of pads should be clipped so you
don't have to worry about silkscreen on top of real pads. I've not used
AC for a long time, so I suppose this should be checked, but they'd be
insane not to do that by default (as everyone else does).

6. Their's a weird blob on silk screen at (2.332,0.426). I believe
that's supposed to be "J8" since I can't find that label anywhere :),
but you should look into that, since that's a weird anomaly.

# Front Side

1. **WARNING** Many of your components' pads are "too close". What this
means is that there is no solder mask between to adjacent pads, so
there's an open "solder channel" between them. This can be a real
problem when reflowing. Usually components get "sucked" into place by
the force of the molten solder.. but if there are other channels for the
solder to flow, there can be torque on components, and they'll literally
flip around right when the solder gets molten. It's ugly. Sometimes
worse, on pads to vias that are too close, the vias will suck the solder
in and leave a dry pad. Examples are:

Vias to U5
C9 to U5
C10, C11 to U6 **and** to the vias
R10 to R11, R11 to C13
J1 to vias
MANY examples of components to vias (e.g., C22)

The way to fix this is to just back off the components enough so that
the solder mask can creep around the pads and vias... it looks like by >

Now I remember you saying you used the board layout from TI for the RF
section - if that's true, then they're insane because they've specified
the components as too close. Or, perhaps they have in mind a tighter
design rule for the solder mask.

2. **WARNING** I'm not sure C4 is actually going to fit where you've
placed. The mini USB connector is awfully close, and the PDF datasheet
shows some stuff there. If you've carefully measured this out, then go
for it, else I'd definitely move that component.

3. Why the keepout around J1-J3? I'd move those FETs closer in, but you
have a silscreen keep out there... are you planning a shield? Or?

## Front Solder Stencil

1. **WARNING** You need to check the stencil mask for U9. I'm pretty
sure they don't want you to coat the entire underside of that pad with
solder. Usually what happens is that the chip will "float" on the solder
and tips to one side. Usually the mfg. will spec four smaller squares
for the cream, leaving the solder room to wick out. Although, I see the
vias under the pads, so perhaps TI thinks that will do the same thing
for them. I'd be very nervous about this, since we've had lots of DFNs
do the "tipping" thing.

## Back solder mask

1. **WARNING** It looks like the back solder mask goes over J8's ground
plane. I'd keep the solder mask off this, so you can solder all four
pins of the SMA connector.

OK, that's enough to keep you busy. even more nit picks soon!


Andrew Greenberg

Portland State Aerospace Society (  P: 503.788.1343  C: 503.708.7711

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