On Wed, 2008-12-24 at 13:14 -0800, Andrew Greenberg wrote:
> # Back solder mask
> 1. Why aren't there keepouts on the solder mask for the vias on U9?
> that's sort of strange.
In the gEDA PCB tool, vias are covered with mask by default, and you
have to explicitly uncover them. I've been doing that by selecting
everything on the via "layer" and applying the command to open up the
mask clearance to the selected group. Since the vias that are part of
the exposed ground land under the CC1111 are actually holes defined in
the part footprint, the tool doesn't see them as vias, and so the
approach I've been using has not uncovered them.
I think the "fix" for that would be to specify a mask clearance on the
holes defined in the footprint. I'll have a look. My suspicion is that
this doesn't really matter, but opening them up makes sense to me, so
I'll see about doing it.
> OK, I need to get real work done now :) If you do a design rev, let me
> know, and I'll re-look at the board.
Thanks a lot for taking the time to have a look! I don't currently plan
to do more than look at the above vias. Unless someone else comes up
with another issue, I'll probably send the artwork off to fab later this
afternoon. AP is closed on the 25th and 1st, but working normal hours
otherwise, so hopefully we'll have raw boards back sometime next week.
> OH: to be explicit, I haven't looked at the schematic very hard. We
> reviewed it once, Glenn, Dan and Eric looked at it, so I think you're
> OK. And there's nothing glaring that I can see.
Right. I've stared at it long enough that I'm not capable of seeing
anything new at this point. The catch on the FET pins being swapped was
wonderful, and definitely worth waiting a couple days for you guys to
help review. My thanks to all of you!
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