I have been working to get v1257 up and running, with some
success.

> sudo /home/kwilson/PSAS/LPCDEV/LPC/2148/OCD/bin/openocd --version
Open On-Chip Debugger 1.0 (2008-12-19-11:49) svn:1257

I noticed this in your output:
current mode: System

and I have

current mode: Supervisor

So, I have attached my cfg and runscript, It may be a script
problem. I think I ran into this before and Dave C. showed me
a fix:

# Force ARM7 into supervisor mode
reg cpsr 0x13

# mww: Memory word write
# Set the MEMMAP reg to point to flash (avoids problems while trying to
#flash)
mww 0xE01FC040 1

Of course, these may have fixed a different issue, or two, but it's
worth a try if you haven't.

I do see some differences between your config and mine:

There are 'sub'-config files in the openocd configuration and
I source the one for the olimex jtag. I don't know if it matters...

#----------- JTAG Interface Type
source [find interface/olimex-arm-usb-ocd.cfg]
jtag_speed  15       # JTAG clock divider

You have a version 17 steps ahead of mine though...

Luck,
 -K



mgross wrote:
> I'm attempting to get back into the lpc2148 efforts again, and I'm
> rebuilding my toolchain and I see that openocd has changed a lot.
> 
> I'm running svn:1274, and it sort of works but I'm getting 
> target state: halted
> target halted in Thumb state due to watchpoint, current mode: System
> cpsr: 0xffffffff pc: 0xffffffef
> Error: invalid mode value encountered
> Error: cpsr contains invalid mode value - communication failure
> target state: halted
> target halted in Thumb state due to watchpoint, current mode: System
> cpsr: 0xffffffff pc: 0xffffffef
> 
> That repeat.
> 
> Does anyone have any ideas on what could be going on?
> 
> Thanks for any ideas.
> 
> Thanks,
> 
> --mgross
> 
> 
> FWIW my openocd.cfg is:
> 
> #daemon configuration
> telnet_port 4444
> gdb_port 3333
> 
> 
> interface ft2232
> ft2232_device_desc "Olimex OpenOCD JTAG"
> ft2232_layout olimex-jtag
> ft2232_vid_pid 0x15ba 0x0003
> 
> if { [info exists CHIPNAME] } { 
>    set  _CHIPNAME $CHIPNAME    
> } else {         
>    set  _CHIPNAME lpc2148
> }
> 
> if { [info exists ENDIAN] } {   
>    set  _ENDIAN $ENDIAN    
> } else {         
>    set  _ENDIAN little
> }
> 
> if { [info exists CPUTAPID ] } {
>    set _CPUTAPID $CPUTAPID
> } else {
>   # force an error till we get a good number
>    set _CPUTAPID 0xffffffff
> }
> 
> #delays on reset lines
> jtag_nsrst_delay 200
> jtag_ntrst_delay 200
> 
> # NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate 
> # JTAG, power-on reset is not enough, i.e. you need to perform a
> # reset before being able to talk to the LPC2148, attach is not
> # possible.
> 
> #use combined on interfaces or targets that can't set TRST/SRST
> separately
> reset_config trst_and_srst srst_pulls_trst
> 
> #jtag scan chain
> jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
> -expected-id $_CPUTAPID
> 
> set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
> target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
> $_TARGETNAME -variant arm7tdmi-s_r4
> $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000
> -work-area-size 0x4000 -work-area-backup 0
> $_TARGETNAME configure -event reset-init {
>         # Force target into ARM state
>         soft_reset_halt
>         #do not remap 0x0000-0x0020 to anything but the flash
>         mwb 0xE01FC040 0x01 
>         
> }
> #working_area 0 0x40000000 0x80000 nobackup
> 
> #flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
> flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
> 
> --mgross
> 
> 
> 
> ------------------------------------------------------------------------
> 
> _______________________________________________
> psas-avionics mailing list
> psas-avionics@lists.psas.pdx.edu
> http://lists.psas.pdx.edu/mailman/listinfo/psas-avionics

#!/usr/bin/expect



set timeout 20 ;# just in case.

set host localhost ;# 127.0.0.0

set port 4444 ;# openocd port

set cwd [pwd]

spawn telnet "$host" "$port";

expect ">"  ;# prompt

send "script $cwd/oocd_flash_lpc2148.script\r";

interact;



# Configuration for the LPC2148
#

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME lpc2148
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
  # force an error till we get a good number
   set _CPUTAPID 0x4f1f0f0f
}

#delays on reset lines
jtag_nsrst_delay 200
jtag_ntrst_delay 200


# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate 
# JTAG, power-on reset is not enough, i.e. you need to perform a
# reset before being able to talk to the LPC2148, attach is not
# possible.

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst

#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 
$_CPUTAPID

set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position 
$_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 
-work-area-size 0x4000 -work-area-backup 0
$_TARGETNAME configure -event reset-init {
        # Force target into ARM state
        soft_reset_halt
        #do not remap 0x0000-0x0020 to anything but the flash
        mwb 0xE01FC040 0x01

}


#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
#flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765


#----------- Daemon Configuration

telnet_port     4444
gdb_port        3333


# Tell gdb that you can use us to program the device (requires GDB >=6.7 and 
libexapt)
gdb_memory_map    enable
gdb_flash_program enable

#----------- JTAG Interface Type
source [find interface/olimex-arm-usb-ocd.cfg]
jtag_speed  15       # JTAG clock divider: No PLL means must be at least 15 
(which is 1/16th clock speed)


# Time to wait before halting
#                 [JTAG #]  [wait in ms]
#run_and_halt_time 0         30
#run_and_halt_time 0         1000

# Force everything to use hardware breakpoints since we're debugging from flash
#arm7_9 force_hw_bkpts enable
gdb_breakpoint_override enable

#-------- Working area (debugging, on-the-fly coding)

# RAM to use when writing to flash (temporary copy)
# locatations from memory map-ram starts at  0x4000 0000
#working_area  [target#]  [address]    [size]   ['backup'|'nobackup']
#working_area   0          0x40000000   0x8000   nobackup

#-------- Flash configuration

#LPC2148 @ 12MHz / 0x80000 from 512*1024...plus/minus 1 issue, lets not push it.
# 0x0008 0000 is reserved address...
#flash bank [driver] [base] [size]  [chip_width] [bus_width] [target#] 
[variant]  [freq] [cksum]
flash  bank lpc2000  0      0x80000 0            0           0         
lpc2000_v2 12000  calc_checksum

 
Here is my openocd_flash_lpc2148.script (much historical kruft, sorry)
Output follows script...

# open ocd (on chip debugger) script to flash lpc2148
# 'info .../OCD/src/openocd/doc/openocd.info'

# 3 is most. 0 is least info.
debug_level 1

# stop
reset halt

# log file
log_output write_flash.log

# pause...500mS
sleep 500

# current state
poll

# Force ARM7 into supervisor mode
reg cpsr 0x13

# mww: Memory word write
# Set the MEMMAP reg to point to flash (avoids problems while trying to
#flash)
mww 0xE01FC040 1

###
# * arm7_9 dcc_downloads <ENABLE|DISABLE> Enable the use of the debug
#     communications channel (DCC) to write larger (>128 byte) amounts
#     of memory. DCC downloads offer a huge speed increase, but might be
#     potentially unsafe, especially with targets running at a very low
#     speed. This command was introduced with OpenOCD rev. 60.
arm7_9 dcc_downloads enable

# Wait for target to enter debug mode. Default time is 5ms.
wait_halt

# pause
sleep 10

# current state
poll

# identify the flash
flash probe 0

# erase first bank only:
flash erase_sector 0 0 26

# pause
sleep 20

# memory display halfword <from address> [COUNT]
mdh 0x0 30

# pause
sleep 20

###
# * flash write_image [ERASE] <FILE> [OFFSET] [TYPE] Write the image
#     <FILE> to the current target's flash bank(s). A relocation
#     [OFFSET] can be specified and the file [TYPE] can be specified
#     explicitly as `bin' (binary), `ihex' (Intel hex), `elf' (ELF file)
#     or `s19' (Motorola s19). Flash memory will be erased prior to
#     programming if the `erase' parameter is given.

flash write_image multiEp.hex 0x0 ihex
#flash write_image race_test.hex 0x0 ihex
#flash write_image serial_dave.hex 0x0 ihex
#flash write_image serial.hex 0x0 ihex

#flash erase write_image serial.hex 0x0
#flash write_image serial.elf 0x0 elf
#flash write_image serial.hex 0x0 ihex
#flash write_image serial.bin 0x0 bin

# pause
sleep 20

# memory display halfword <from address> [COUNT]
mdh 0x0 30

# pause
sleep 20

# can't verify because of 0x14 reserved chksum address (LPC SPEC)
#verify_image serial.hex 0x0 bin

# memory display halfword <from address> [COUNT]
mdh 0x0 30

# pause
sleep 20

#reset run_and_halt
reset

# pause
sleep 10

# stop the open ocd daemon.
#shutdown


=================
> script 
> /home/kwilson/PSAS/PSASGIT/node-usb/target/examples/oocd_flash_lpc2148.script
 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
 target state: halted
 target halted in Thumb state due to debug-request, current mode: Supervisor
 cpsr: 0xa00000f3 pc: 0x7fffd2c0
 target state: halted
 target halted in Thumb state due to debug-request, current mode: Supervisor
 cpsr: 0xa00000f3 pc: 0x7fffd2c0
 cpsr (/32): 0x00000013
             dcc downloads are enabled
             target state: halted
             target halted in ARM state due to debug-request, current mode: 
Supervisor
             cpsr: 0x00000013 pc: 0x7fffd2c0
             flash 'lpc2000' found at 0x00000000
             erased sectors 0 through 26 on flash bank 0 in 0.724949s
             0x00000000: ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 
ffff ffff ffff ffff ffff 
             0x00000020: ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 
ffff ffff ffff 
             No flash at address 0x7fd00000

             wrote 9176 byte from file multiEp.hex in 2.188057s (4.095386 kb/s)
  0x00000000: f018 e59f f018 e59f f018 e59f f018 e59f f018 e59f 5f84 b920 fff0 
e51f f014 e59f 
  0x00000020: 0040 0000 00e4 0000 00e0 0000 00e4 0000 00e4 0000 00d8 0000 00dc 
0000 
  0x00000000: f018 e59f f018 e59f f018 e59f f018 e59f f018 e59f 5f84 b920 fff0 
e51f f014 e59f 
  0x00000020: 0040 0000 00e4 0000 00e0 0000 00e4 0000 00e4 0000 00d8 0000 00dc 
0000 

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