Very good questions.
The PSAS library has evolved over time, but it has not been consistently
maintained. One result of this is that most of the packages don't
follow current best practices.
Of course we want new packages to be more up-to-date.
I looked around a bit for a decent example, i found a reasonably good
example in the Eagle maxim.lbr. This library is included in the default
Eagle installation. There are some bad packages in this library as well,
but check out the "UMAX10" package.
The most important thing to get right are the surface mount lands (aka
"footprint"). These are never the same size as the package leads because
of tolerance and alignment considerations.
Usually the manufacturer has a suggested land pattern arrangement. Often
this is included in the datasheet. If not standard land patterns are
The tPlace layer (layer 21) is for package placement aids. Usually this
includes a package outline or package registration marks and a
polarizing mark if required.
The wires on tPlace end up on the silkscreen of the PCB. The silkscreen
only exists on top of the solder mask, so no tPlace marks can exist over
package lands. It's good practice to keep the silkscreen at least 0.25 mm
away from any lands.
The tDocu layer (layer 51) is not transferred to any feature of the PCB.
Usually it is used to convey placement information in the board editor
that will not be transferred to the PCB. Typically this includes lead
silhouettes, package outlines over lands, or miscellaneous identifying
marks visible on the package.
I recommend simple, clear, but minimal graphics on tPlace. Pin
silhouettes and full package outlines on tDocu.
Also include a >NAME, >VALUE, and "Description" for each package.
This is a complex topic, so feel free to ask more questions.
> Hi all,
> This may be a goofy question, but I'm unclear on the matter so I'll ask it
> anyway... I've noticed that many of the existing parts in the psas EAGLE
> library have pins represented in both the top layer and tplace layer. I'm
> guessing that the tplace layer pin represents the physical pin and the top
> layer representation is the footprint. Is this correct, and should we be
> doing this as we create new ICs in EAGLE? thus far I've only used the smd
> function for pins, but it wouldn't be too hard to add rectangles using the
> tplace layer.
> On the same note, I also notice that the dimensions of the pins in the top
> layer seem different than those drawn with the tPlace layer. Is this
> difference in dimension represented somehow in the datasheet?
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