Thanks for the feedback Tim,
I've fixed the issue with the ground return paths on the TPS63000 (I think).  
As for the other problems, they'll take me a bit more time to figure out what I 
want to rearrange.

As for the 0kaz library, I have added it to git so you can review any of the 
packages I have made so far if you like.

The SJ280 width errors I have been meaning to ask about. I think they are 
cuttable jumpers, can I set that width to anything I want, or is there a 
reasonable maximum for a cuttable trace width?

Thanks,
Ken


----- Original Message ----
From: "rq1...@q7.com" <rq1...@q7.com>
To: psas-avionics@lists.psas.pdx.edu
Sent: Sunday, May 24, 2009 5:18:44 PM
Subject: Re: [psas-avionics] Capstone Generic node update

(2009.05.23) kenz...@yahoo.com:
> Ok, so I have made some progress today on the layout for the front end. 
> I still haven't added any polygons for ground or power planes yet,
> everything is still coming together somewhat.? At least I finally have
> all the components on the board.If any of you have time, could you
> please review what I have so far so I can have changes ready by
> Tuesday? The files are node5-frontend.sch and node5-frontend.brd for
> the schematic and board.

I think pretty good so far :)

There are a couple "width" errors in the DRC you should probably fix,
e.g. SJ280
      WINDOW 5 (2745 1481);

It's good practice to equalize the gaps between signals, cf. to the
right of C13
      SHOW @ C13

I personally think the battery should be on the bottom of the board.
Andrew, i believe, agrees. In fact he had mentioned putting the battery
on a sub-carrier board that would screw onto the main node board. The
actual battery connection made with some convenient board to board
connector, JST, 2 mm, etc.

I haven't analyzed the switching power supplies, but at frequencies
above 1 MHz ground return path becomes a significant consideration. It
is possible to handle all your ground returns with vias into the ground
plane, and that may be acceptable, but for certain critical paths it is
better to route entirely on the component plane.

For example, U2203 & C2221, the capacitor is the input bypass for the
switcher running at 1.5 MHz. The signal to be bypassed is
PROTECTED_DC_POWER, which is actually adjacent to the grounded pad of
the chip, but the grounded end of the capacitor is too far away to
effectively reach the pad. I think TI intended that C2211 sit directly
over the chip so as to make the direct connection to the pad.

The principle of providing very short paths for signals that are both
high frequency and high current applies to all the switching supplies.
You should keep this in mind during layout.

I think what is driving the placement of C2221 is the fact that you have
laid out without much regard to ground connection distance. This is
generally the right thing to do if you have a ground plane. The
exception would be the critical paths associated with the switching
supplies.

----

There is a funny thing going on with U2203 where some of the traces
running into the pad are generating "overlap" errors. I can't really
evaluate this because your private library "0kaz" does not seem to be in
git. It should be.

----

Mostly things seem pretty reasonable.

Have you coordinated with Scott on APS real estate allocation? It looks
roughly right to me but i suspect you'll need to push leftward a bit.

I'm pretty busy 'til Tuesday, but if you have more questions, fire away,
i'll try :)


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