Ok, I've looked over what I understand to be the latest GFE layout a few
times. This would be node5-frontend.*
Question Barrage Commencing:
Is there an assumed ground plane a-la "polygon", and if so, would this then
be done as the last thing before producing the gerber and other production
How many layers are available? I saw something I assumed to be a jumper to
be soldered later, but it is in layer 15. It appears that traces may be run
in layers 2 and 15, in addition to 1 and 16, thus a 4 layer board. We are
currently using 3 layers, are 4 available? How far should I leverage 2 and
15? And what's with all the loose vias all over? Are they tied to
something spooky I can't see?
Pins and Parts. I note that many of the LPC pins are currently dangling. I
see that many of them lead to "con_itty_bitty_pad" things. What's the
scoop? Do we want these to have leads going off to the "right hand" side of
the board, or is there something else going on where we'll use these
"pads"? Also, it looks like there are some heavy traces for unmarked parts,
or some other connection. What's going on with these?
Design Rules. Do we have a design rules file floating about? Do we have
different files for different purposes/fab options? Where would such a
thing live, or where would be the relevant data to correct my design rules
file. Also, PSAS custom parts library. I think I saw that floating about.
I bet I even have it. I can't reach my personal PC just now, but can
someone point out the filename(s)?
What more does this board need? It looks good and the parts are all there.
I heard something about Refactoring and re"Repacking". Is the implication
here to condense the listed parts further to the "left hand" side of the
board to maximize available node space? Should I smash labels, and what
should remain and what should not? I'm guessing strip part labels out
almost entirely, and replace them with Human Readable debugging info "USB
goes here" "Positive 5V here" "Wet Paint" "No Trespassing" etc.
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