Hi, I am simulating a hardware system with DE domain, and a following
message appears now and then:
XOR1.output lies on a delay-free loop.
I think this is because I use the output of the system as one of its
previous steps, and ptolemy becomes crazy in those cases. The only way in
which I have been able to solve it is to introduce a delay between the
output and the point of the previous step to which it is connected. The
smallest delay that has worked is 0.5. I hope you have understood.
My question is: Is there a way of avoiding that, of making the system
without introducing this delay element?
thanks
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