https://bugs.freedesktop.org/show_bug.cgi?id=49608
--- Comment #51 from Raymond <[email protected]> --- https://www.google.com/patents/US20100131783 FIG. 2 illustrates an exemplary FIFO which has a FIFO size of 192 bytes, and a threshold value of 128 bytes. Taking 48 kHz sample rate, 2 channels each having 16 bits (or 2 bytes) for example, each frame thus contains 4 bytes of data, wherein each frame is regarded as a “data unit of transportation.” Whenever the amount of stream data in the FIFO is less than 128 bytes (i.e., the threshold), the HDAC 15 will issue a bus mater cycle. As each frame is transported in an interval time of 20.83 micro second (μs) (=1/(48×103)), which is regarded as a “time unit of transportation,” the 128 bytes therefore can keep 32 frames (=128/4) of data for about 666 micro second (=32×20.83) without under run. you need to use 32bits or more channels, higher rate to get 0.5ms latency -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.
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