Hi,
I’m trying to figure out how to load FPGA bitstreams through the pretty
PyOpenCL frontend.
Some notes from my experiments:
https://paper.dropbox.com/doc/PyOpenCL-for-Xilinx-FPGAs-tT2KOlxwe2YGWNBdKNyzx
<https://paper.dropbox.com/doc/PyOpenCL-for-Xilinx-FPGAs-tT2KOlxwe2YGWNBdKNyzx>
https://paper.dropbox.com/doc/PyOpenCL-with-Altera-FPGAs-8ojfCVUBhiz7UOjRTIaFe
<https://paper.dropbox.com/doc/PyOpenCL-with-Altera-FPGAs-8ojfCVUBhiz7UOjRTIaFe>
I’ve also setup a fork at https://github.com/nachiket/pyopencl
<https://github.com/nachiket/pyopencl> with “altera” and “xilinx” branches with
the correct paths.
In both cases, I’m unable to get the APIs to work (error messages are in the
notes above). I appreciate any pointers you might have.
Nachiket
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