Author: hager <sven.ha...@uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r46757:fb5b36c4d073
Date: 2011-08-24 13:29 +0200
http://bitbucket.org/pypy/pypy/changeset/fb5b36c4d073/
Log: merge
diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
@@ -484,6 +484,9 @@
srawi = Form("rA", "rS", "SH", "XO1", "Rc")(31, XO1=824, Rc=0)
srawix = Form("rA", "rS", "SH", "XO1", "Rc")(31, XO1=824, Rc=1)
+ srd = XS(31, XO1=539, Rc=0)
+ srdx = XS(31, XO1=539, Rc=1)
+
srw = XS(31, XO1=536, Rc=0)
srwx = XS(31, XO1=536, Rc=1)
@@ -581,9 +584,13 @@
# F.3 Simplified Mnemonics for Compare Instructions
+ cmpdi = BA.cmpi(L=1)
cmpwi = BA.cmpi(L=0)
+ cmpldi = BA.cmpli(L=1)
cmplwi = BA.cmpli(L=0)
+ cmpd = BA.cmp(L=1)
cmpw = BA.cmp(L=0)
+ cmpld = BA.cmpl(L=1)
cmplw = BA.cmpl(L=0)
# F.4 Simplified Mnemonics for Rotate and Shift Instructions
@@ -618,6 +625,9 @@
def sldi(self, rA, rS, n):
self.rldicr(rA, rS, n, 63-n)
+ def srdi(self, rA, rS, n):
+ self.rldicl(rA, rS, 64-n, n)
+
# F.5 Simplified Mnemonics for Branch Instructions
# there's a lot of these!
@@ -899,29 +909,31 @@
PPCAssembler.__init__(self)
def load_word(self, rD, word):
- self.addis(rD, 0, hi(word))
- self.ori(rD, rD, lo(word))
+ if IS_PPC_32:
+ self.lis(rD, hi(word))
+ self.ori(rD, rD, lo(word))
+ else:
+ self.lis(rD, highest(word))
+ self.ori(rD, rD, higher(word))
+ self.sldi(rD, rD, 32)
+ self.oris(rD, rD, high(word))
+ self.ori(rD, rD, lo(word))
def load_from(self, rD, addr):
if IS_PPC_32:
self.addis(rD, 0, ha(addr))
+ self.lwz(rD, rD, la(addr))
else:
- self.addis(rD, 0, highest(addr))
- self.ori(rD, rD, higher(addr))
- self.sldi(rD, rD, 32)
- self.oris(rD, rD, high(addr))
- self.lwz(rD, rD, la(addr))
+ self.load_word(rD, addr)
+ self.ld(rD, rD, 0)
def store_reg(self, source_reg, addr):
- self.load_word(10, addr)
- self.stw(source_reg, 10, 0)
-
- def load_dword(self, rD, dword):
- self.addis(rD, 0, highest(dword))
- self.ori(rD, rD, higher(dword))
- self.sldi(rD, rD, 32)
- self.oris(rD, rD, high(dword))
- self.ori(rD, rD, lo(dword))
+ if IS_PPC_32:
+ self.addis(10, 0, ha(addr))
+ self.stw(source_reg, 10, la(addr))
+ else:
+ self.load_word(10, addr)
+ self.std(source_reg, 10, 0)
# translate a trace operation to corresponding machine code
def build_op(self, trace_op, cpu):
@@ -1028,17 +1040,31 @@
def emit_int_mul(self, op, cpu, reg0, reg1, free_reg):
# XXX need to care about factors whose product needs 64 bit
- self.mullw(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.mullw(free_reg, reg0, reg1)
+ else:
+ self.mulld(free_reg, reg0, reg1)
def emit_int_mul_ovf(self, op, cpu, reg0, reg1, free_reg):
- self.mullwo(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.mullwo(free_reg, reg0, reg1)
+ else:
+ self.mulldo(free_reg, reg0, reg1)
def emit_int_floordiv(self, op, cpu, reg0, reg1, free_reg):
- self.divw(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.divw(free_reg, reg0, reg1)
+ else:
+ self.divd(free_reg, reg0, reg1)
def emit_int_mod(self, op, cpu, reg0, reg1, free_reg):
- self.divw(free_reg, reg0, reg1)
- self.mullw(free_reg, free_reg, reg1)
+ if IS_PPC_32:
+ self.divw(free_reg, reg0, reg1)
+ # use shift left of log2
+ self.mullw(free_reg, free_reg, reg1)
+ else:
+ self.divd(free_reg, reg0, reg1)
+ self.mulld(free_reg, free_reg, reg1)
self.subf(free_reg, free_reg, reg0)
def emit_int_and(self, op, cpu, reg0, reg1, free_reg):
@@ -1051,46 +1077,72 @@
self.xor(free_reg, reg0, reg1)
def emit_int_lshift(self, op, cpu, reg0, reg1, free_reg):
- self.slw(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.slw(free_reg, reg0, reg1)
+ else:
+ self.sld(free_reg, reg0, reg1)
def emit_int_rshift(self, op, cpu, reg0, reg1, free_reg):
- self.sraw(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.sraw(free_reg, reg0, reg1)
+ else:
+ self.srad(free_reg, reg0, reg1)
def emit_uint_rshift(self, op, cpu, reg0, reg1, free_reg):
- self.srw(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.srw(free_reg, reg0, reg1)
+ else:
+ self.srd(free_reg, reg0, reg1)
def emit_uint_floordiv(self, op, cpu, reg0, reg1, free_reg):
- self.divwu(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.divwu(free_reg, reg0, reg1)
+ else:
+ self.divdu(free_reg, reg0, reg1)
def emit_int_eq(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
- self.mfcr(free_reg)
- self.rlwinm(free_reg, free_reg, 31, 31, 31)
+ self.xor(free_reg, reg0, reg1)
+ if IS_PPC_32:
+ self.cntlzw(free_reg, free_reg)
+ self.srwi(free_reg, free_reg, 5)
+ else:
+ self.cntlzd(free_reg, free_reg)
+ self.srdi(free_reg, free_reg, 6)
def emit_int_le(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.cror(31, 30, 28)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 0, 31, 31)
def emit_int_lt(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 29, 31, 31)
def emit_int_ne(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
- self.crnot(30, 30)
- self.mfcr(free_reg)
- self.rlwinm(free_reg, free_reg, 31, 31, 31)
+ self.emit_int_eq(op, cpu, reg0, reg1, free_reg)
+ self.xori(free_reg, free_reg, 1)
def emit_int_gt(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 30, 31, 31)
def emit_int_ge(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.cror(31, 30, 29)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 0, 31, 31)
@@ -1176,14 +1228,16 @@
self.sub(free_reg, free_reg, reg0)
def emit_int_invert(self, op, cpu, reg0, free_reg):
- self.load_word(free_reg, -1)
+ self.li(free_reg, -1)
self.xor(free_reg, free_reg, reg0)
def emit_int_is_zero(self, op, cpu, reg0, free_reg):
- self.xor(free_reg, free_reg, free_reg)
- self.cmp(7, free_reg, reg0)
- self.mfcr(free_reg)
- self.rlwinm(free_reg, free_reg, 31, 31, 31)
+ if IS_PPC_32:
+ self.cntlzw(free_reg, reg0)
+ self.srwi(free_reg, free_reg, 5)
+ else:
+ self.cntlzd(free_reg, reg0)
+ self.srdi(free_reg, free_reg, 6)
def emit_guard_true(self, op, cpu):
arg0 = op.getarg(0)
diff --git a/pypy/jit/backend/ppc/ppcgen/test/test_ppc.py
b/pypy/jit/backend/ppc/ppcgen/test/test_ppc.py
--- a/pypy/jit/backend/ppc/ppcgen/test/test_ppc.py
+++ b/pypy/jit/backend/ppc/ppcgen/test/test_ppc.py
@@ -178,8 +178,6 @@
a.blr()
def test_call_function(self):
- if is_64_bit_arch():
- py.test.skip("call 64 bit")
functype = lltype.Ptr(lltype.FuncType([lltype.Signed], lltype.Signed))
call_addr = rffi.cast(lltype.Signed, llhelper(functype, func))
a = PPCBuilder()
@@ -192,7 +190,12 @@
# - Do jump
a.li(3, 50)
- a.load_word(10, call_addr)
+ if IS_PPC_32:
+ a.load_word(10, call_addr)
+ else:
+ a.load_from(10, call_addr)
+ a.load_from(2, call_addr+WORD)
+ a.load_from(11, call_addr+2*WORD)
a.mtctr(10)
a.bctr()
a.blr()
@@ -270,12 +273,8 @@
a.load_word(10, word1)
a.load_word(11, word2)
- if IS_PPC_64:
- a.load_dword(8, rffi.cast(lltype.Signed, p))
- a.load_dword(9, rffi.cast(lltype.Signed, p) + WORD)
- else:
- a.load_word(8, rffi.cast(lltype.Signed, p))
- a.load_word(9, rffi.cast(lltype.Signed, p) + WORD)
+ a.load_word(8, rffi.cast(lltype.Signed, p))
+ a.load_word(9, rffi.cast(lltype.Signed, p) + WORD)
a.stw(10, 8, 0)
a.stw(11, 9, 0)
@@ -290,35 +289,18 @@
def test_load_from(self):
a = PPCBuilder()
- p = lltype.malloc(rffi.CArray(rffi.INT), 1, flavor="raw")
+ p = lltype.malloc(rffi.CArray(rffi.LONG), 1, flavor="raw")
addr = rffi.cast(lltype.Signed, p)
- p[0] = rffi.cast(rffi.INT, 200)
+ p[0] = rffi.cast(rffi.LONG, 200)
a.load_from(3, addr)
a.blr()
f = a.assemble()
assert f() == 200
- p[0] = rffi.cast(rffi.INT, 300)
+ p[0] = rffi.cast(rffi.LONG, 300)
assert f() == 300
lltype.free(p, flavor="raw")
- def test_ld(self):
- if not is_64_bit_arch():
- py.test.skip("works on 64 bit")
- a = PPCBuilder()
-
- p = lltype.malloc(rffi.CArray(rffi.LONG), 1, flavor="raw")
- addr = rffi.cast(lltype.Signed, p)
- p[0] = rffi.cast(rffi.LONG, 200)
-
- a.load_dword(3, addr)
- a.ld(3, 3, 0)
- a.blr()
-
- f = a.assemble()
- assert f() == 200
- lltype.free(p, flavor="raw")
-
class AsmCode(object):
def __init__(self, size):
@@ -341,7 +323,7 @@
def is_64_bit_arch():
import sys
return sys.maxint == 9223372036854775807
-
+
"""
class TestAssemble(object):
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