Author: David Schneider <david.schnei...@picle.org>
Branch: arm-backend-2
Changeset: r47706:ffb8697a5a63
Date: 2011-09-29 14:23 +0200
http://bitbucket.org/pypy/pypy/changeset/ffb8697a5a63/
Log: also support REF types
diff --git a/pypy/jit/backend/arm/assembler.py
b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -881,7 +881,7 @@
raise AssertionError("mov reg to imm doesn't make sense")
if loc.is_reg():
self.mc.MOV_rr(loc.value, prev_loc.value, cond=cond)
- elif loc.is_stack() and loc.type == INT:
+ elif loc.is_stack() and loc.type != FLOAT:
# spill a core register
offset = ConstInt(loc.position*WORD)
if not _check_imm_arg(offset, size=0xFFF):
@@ -897,7 +897,7 @@
def _mov_stack_to_loc(self, prev_loc, loc, cond=c.AL):
pushed = False
if loc.is_reg():
- assert prev_loc.type == INT, 'trying to load from an incompatible
location into a core register'
+ assert prev_loc.type != FLOAT, 'trying to load from an
incompatible location into a core register'
# unspill a core register
offset = ConstInt(prev_loc.position*WORD)
if not _check_imm_arg(offset, size=0xFFF):
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